From 2458b38772c63b27e52189aa0a363802a69b7cc7 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 4 Jun 2024 12:51:12 +0100 Subject: [PATCH 1/3] refactor(tc): append binding for SMMU-700 The usage for SMMU-700 is not consistent across TC platforms: SMMU-700 on TC2: | FVP | FPGA --------+-------+------ Display | Used | Used GPU | Used | Used SMMU-700 on TC3: | FVP | FPGA --------+-------+------ Display | No | No GPU | Used | No This commit changes to use append mode for SMMU-700 to bind it on TC2 and TC3 separately. As a result, the TC_IOMMU_EN configuration is not used, remove it. Change-Id: Ic4152eb4c8ef97bf27b8a97c3c6cb86e32a2e8eb Signed-off-by: Leo Yan --- fdts/tc-base.dtsi | 9 +-------- fdts/tc2.dts | 9 +++++++++ fdts/tc3.dts | 12 ++++++++++++ plat/arm/board/tc/platform.mk | 3 --- 4 files changed, 22 insertions(+), 11 deletions(-) diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi index 494c825df..344979243 100644 --- a/fdts/tc-base.dtsi +++ b/fdts/tc-base.dtsi @@ -482,9 +482,6 @@ scmi-perf-domain = <3>; #endif /* TC_SCMI_PD_CTRL_EN */ -#if TC_IOMMU_EN - iommus = <&smmu_700 0x200>; -#endif /* TC_IOMMU_EN */ pbha { int-id-override = <0 0x22>, <2 0x23>, <4 0x23>, <7 0x22>, <8 0x22>, <9 0x22>, <10 0x22>, <11 0x22>, @@ -507,7 +504,6 @@ thermal-zone = ""; }; -#if TC_IOMMU_EN smmu_700: iommu@3f000000 { #iommu-cells = <1>; compatible = "arm,smmu-v3"; @@ -517,8 +513,8 @@ ; interrupt-names = "eventq", "cmdq-sync", "gerror"; dma-coherent; + status = "disabled"; }; -#endif /* TC_IOMMU_EN */ dp0: display@DPU_ADDR { #address-cells = <1>; @@ -528,9 +524,6 @@ interrupts = ; interrupt-names = "DPU"; DPU_CLK_ATTR1; -#if TC_IOMMU_EN - iommus = <&smmu_700 0x100>; -#endif /* TC_IOMMU_EN */ pl0: pipeline@0 { reg = <0>; diff --git a/fdts/tc2.dts b/fdts/tc2.dts index 69c688601..4946acaae 100644 --- a/fdts/tc2.dts +++ b/fdts/tc2.dts @@ -237,9 +237,18 @@ }; }; + smmu_700: iommu@3f000000 { + status = "okay"; + }; + dp0: display@DPU_ADDR { #if TC_SCMI_PD_CTRL_EN power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>; #endif + iommus = <&smmu_700 0x100>; + }; + + gpu: gpu@2d000000 { + iommus = <&smmu_700 0x200>; }; }; diff --git a/fdts/tc3.dts b/fdts/tc3.dts index fe6a69562..64546b68f 100644 --- a/fdts/tc3.dts +++ b/fdts/tc3.dts @@ -85,4 +85,16 @@ shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>; }; }; + +#if TARGET_FLAVOUR_FVP + smmu_700: iommu@3f000000 { + status = "okay"; + }; +#endif + + gpu: gpu@2d000000 { +#if TARGET_FLAVOUR_FVP + iommus = <&smmu_700 0x200>; +#endif + }; }; diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk index cd5abd013..28b98c281 100644 --- a/plat/arm/board/tc/platform.mk +++ b/plat/arm/board/tc/platform.mk @@ -10,8 +10,6 @@ TARGET_FLAVOUR := fvp TC_DPU_USE_SCMI_CLK := 1 # SCMI power domain control enable TC_SCMI_PD_CTRL_EN := 1 -# IOMMU: Enable the use of system or individual MMUs -TC_IOMMU_EN := 1 # System setup CSS_USE_SCMI_SDS_DRIVER := 1 @@ -76,7 +74,6 @@ $(eval $(call add_defines, \ TC_RESOLUTION_$(call uppercase,${TC_RESOLUTION}) \ TC_DPU_USE_SCMI_CLK \ TC_SCMI_PD_CTRL_EN \ - TC_IOMMU_EN \ )) CSS_LOAD_SCP_IMAGES := 1 From 0458d3acae25aa98f28bc0e0aa578fdce7ae92fa Mon Sep 17 00:00:00 2001 From: Jackson Cooper-Driver Date: Tue, 4 Jun 2024 13:15:00 +0100 Subject: [PATCH 2/3] feat(tc): bind SMMU-700 with DPU on TC3 TC3 adds a new SMMU-700 specifically for the DPU. This is used as the DPU SMMU instead of the existing SMMU used for the DPU. Update the device tree to reflect this. Change-Id: I865140f8f53bceaa8849f6583190b240eeee0539 Signed-off-by: Jackson Cooper-Driver Signed-off-by: Leo Yan --- fdts/tc-base.dtsi | 12 ++++++++++++ fdts/tc3.dts | 11 +++++++++++ 2 files changed, 23 insertions(+) diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi index 344979243..918c49654 100644 --- a/fdts/tc-base.dtsi +++ b/fdts/tc-base.dtsi @@ -516,6 +516,18 @@ status = "disabled"; }; + smmu_700_dpu: iommu@4002a00000 { + #iommu-cells = <1>; + compatible = "arm,smmu-v3"; + reg = ; + interrupts = , + , + ; + interrupt-names = "eventq", "cmdq-sync", "gerror"; + dma-coherent; + status = "disabled"; + }; + dp0: display@DPU_ADDR { #address-cells = <1>; #size-cells = <0>; diff --git a/fdts/tc3.dts b/fdts/tc3.dts index 64546b68f..03542172d 100644 --- a/fdts/tc3.dts +++ b/fdts/tc3.dts @@ -90,8 +90,19 @@ smmu_700: iommu@3f000000 { status = "okay"; }; + + smmu_700_dpu: iommu@4002a00000 { + status = "okay"; + }; #endif + dp0: display@DPU_ADDR { +#if TARGET_FLAVOUR_FVP + iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>, + <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>; +#endif + }; + gpu: gpu@2d000000 { #if TARGET_FLAVOUR_FVP iommus = <&smmu_700 0x200>; From 4c6960ca4040e5628874f48576170b6f8f3904a9 Mon Sep 17 00:00:00 2001 From: Ben Horgan Date: Tue, 4 Jun 2024 13:22:53 +0100 Subject: [PATCH 3/3] feat(tc): bind SMMU-600 with the DPU on TC3 FPGA The SMMU 600 is used on TC3 FPGA board with the display device, add the device tree binding for it. Change-Id: Iadf85873720ca47bbbda999aa7b18a9db98ae945 Signed-off-by: Ben Horgan Signed-off-by: Leo Yan --- fdts/tc-base.dtsi | 12 ++++++++++++ fdts/tc3.dts | 8 ++++++++ 2 files changed, 20 insertions(+) diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi index 918c49654..2e03be2eb 100644 --- a/fdts/tc-base.dtsi +++ b/fdts/tc-base.dtsi @@ -504,6 +504,18 @@ thermal-zone = ""; }; + smmu_600: smmu@2ce00000 { + compatible = "arm,smmu-v3"; + reg = <0 0x2ce00000 0 0x20000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + #iommu-cells = <1>; + status = "disabled"; + }; + smmu_700: iommu@3f000000 { #iommu-cells = <1>; compatible = "arm,smmu-v3"; diff --git a/fdts/tc3.dts b/fdts/tc3.dts index 03542172d..ef0f71a30 100644 --- a/fdts/tc3.dts +++ b/fdts/tc3.dts @@ -94,12 +94,20 @@ smmu_700_dpu: iommu@4002a00000 { status = "okay"; }; +#else + smmu_600: smmu@2ce00000 { + status = "okay"; + }; #endif dp0: display@DPU_ADDR { #if TARGET_FLAVOUR_FVP iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>, <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>; +#else /* TARGET_FLAVOUR_FPGA */ + iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>, + <&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>, + <&smmu_600 8>, <&smmu_600 9>; #endif };