mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 10:04:26 +00:00
Add support to indicate size and end of assembly functions
In order for the symbol table in the ELF file to contain the size of functions written in assembly, it is necessary to report it to the assembler using the .size directive. To fulfil the above requirements, this patch introduces an 'endfunc' macro which contains the .endfunc and .size directives. It also adds a .func directive to the 'func' assembler macro. The .func/.endfunc have been used so the assembler can fail if endfunc is omitted. Fixes ARM-Software/tf-issues#295 Change-Id: If8cb331b03d7f38fe7e3694d4de26f1075b278fc Signed-off-by: Kévin Petit <kevin.petit@arm.com>
This commit is contained in:
Kévin Petit
parent
cd31914246
commit
8b779620d3
32 changed files with 149 additions and 2 deletions
bl1/aarch64
bl2/aarch64
bl31/aarch64
bl32/tsp/aarch64
common/aarch64
drivers/arm/pl011
include/common
lib
aarch64
cpus/aarch64
locks/exclusive
semihosting/aarch64
plat
common/aarch64
fvp/aarch64
juno/aarch64
services
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@ -172,3 +172,4 @@ func bl1_entrypoint
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bl bl1_main
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panic:
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b panic
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endfunc bl1_entrypoint
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@ -124,3 +124,4 @@ func bl2_entrypoint
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bl bl2_main
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_panic:
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b _panic
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endfunc bl2_entrypoint
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@ -200,3 +200,4 @@ func bl31_entrypoint
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bl bl31_main
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b el3_exit
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endfunc bl31_entrypoint
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@ -117,6 +117,7 @@ func el1_sysregs_context_save
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str x15, [x0, #CTX_FP_FPEXC32_EL2]
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ret
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endfunc el1_sysregs_context_save
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/* -----------------------------------------------------
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* The following function strictly follows the AArch64
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@ -205,6 +206,7 @@ func el1_sysregs_context_restore
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/* No explict ISB required here as ERET covers it */
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ret
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endfunc el1_sysregs_context_restore
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/* -----------------------------------------------------
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* The following function follows the aapcs_64 strictly
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@ -249,6 +251,7 @@ func fpregs_context_save
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str x10, [x0, #CTX_FP_FPCR]
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ret
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endfunc fpregs_context_save
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/* -----------------------------------------------------
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* The following function follows the aapcs_64 strictly
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@ -298,4 +301,5 @@ func fpregs_context_restore
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*/
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ret
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endfunc fpregs_context_restore
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#endif /* CTX_INCLUDE_FPREGS */
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@ -51,6 +51,7 @@ func init_cpu_data_ptr
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bl _cpu_data_by_mpidr
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msr tpidr_el3, x0
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ret x10
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endfunc init_cpu_data_ptr
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/* -----------------------------------------------------------------
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@ -68,6 +69,7 @@ func _cpu_data_by_mpidr
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bl platform_get_core_pos
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mov x30, x9
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b _cpu_data_by_index
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endfunc _cpu_data_by_mpidr
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/* -----------------------------------------------------------------
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@ -83,3 +85,4 @@ func _cpu_data_by_index
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adr x1, percpu_data
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add x0, x1, x0, LSL #CPU_DATA_LOG2SIZE
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ret
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endfunc _cpu_data_by_index
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@ -85,6 +85,7 @@ intr_excpt_msg:
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func print_newline
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mov x0, '\n'
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b plat_crash_console_putc
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endfunc print_newline
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/*
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* Helper function to print from crash buf.
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@ -122,6 +123,7 @@ test_size_list:
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exit_size_print:
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mov x30, sp
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ret
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endfunc size_controlled_print
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/*
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* Helper function to store x8 - x15 registers to
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@ -140,6 +142,7 @@ func str_in_crash_buf_print
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stp x12, x13, [x0, #REG_SIZE * 4]
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stp x14, x15, [x0, #REG_SIZE * 6]
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b size_controlled_print
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endfunc str_in_crash_buf_print
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/* ------------------------------------------------------
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* This macro calculates the offset to crash buf from
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@ -176,6 +179,7 @@ func report_unhandled_exception
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mov sp, x0
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/* This call will not return */
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b do_crash_reporting
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endfunc report_unhandled_exception
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/* -----------------------------------------------------
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@ -192,6 +196,7 @@ func report_unhandled_interrupt
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mov sp, x0
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/* This call will not return */
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b do_crash_reporting
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endfunc report_unhandled_interrupt
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/* -----------------------------------------------------
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* This function allows to report a crash (if crash
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@ -208,6 +213,7 @@ func el3_panic
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mov sp, x0
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/* This call will not return */
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b do_crash_reporting
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endfunc el3_panic
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/* ------------------------------------------------------------
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* The common crash reporting functionality. It requires x0
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@ -346,13 +352,16 @@ func do_crash_reporting
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/* Done reporting */
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b crash_panic
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endfunc do_crash_reporting
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#else /* CRASH_REPORTING */
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func report_unhandled_exception
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report_unhandled_interrupt:
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b crash_panic
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endfunc report_unhandled_exception
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#endif /* CRASH_REPORING */
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func crash_panic
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b crash_panic
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endfunc crash_panic
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@ -479,6 +479,7 @@ smc_prohibited:
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rt_svc_fw_critical_error:
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msr spsel, #1 /* Switch to SP_ELx */
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bl report_unhandled_exception
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endfunc smc_handler
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/* -----------------------------------------------------
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* The following functions are used to saved and restore
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@ -503,6 +504,7 @@ func save_gp_registers
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stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
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save_x18_to_x29_sp_el0
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ret
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endfunc save_gp_registers
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func restore_gp_registers_eret
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ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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@ -525,3 +527,4 @@ restore_gp_registers_callee_eret:
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msr sp_el0, x17
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ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
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eret
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endfunc restore_gp_registers_eret
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@ -149,6 +149,7 @@ func tsp_entrypoint
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tsp_entrypoint_panic:
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b tsp_entrypoint_panic
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endfunc tsp_entrypoint
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/* -------------------------------------------
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@ -166,6 +167,7 @@ func tsp_vector_table
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b tsp_fiq_entry
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b tsp_system_off_entry
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b tsp_system_reset_entry
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endfunc tsp_vector_table
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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@ -180,6 +182,7 @@ func tsp_vector_table
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func tsp_cpu_off_entry
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bl tsp_cpu_off_main
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restore_args_call_smc
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endfunc tsp_cpu_off_entry
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when the
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@ -191,6 +194,7 @@ func tsp_cpu_off_entry
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func tsp_system_off_entry
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bl tsp_system_off_main
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restore_args_call_smc
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endfunc tsp_system_off_entry
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when the
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@ -202,6 +206,7 @@ func tsp_system_off_entry
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func tsp_system_reset_entry
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bl tsp_system_reset_main
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restore_args_call_smc
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endfunc tsp_system_reset_entry
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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@ -292,6 +297,7 @@ func tsp_cpu_on_entry
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/* Should never reach here */
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tsp_cpu_on_entry_panic:
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b tsp_cpu_on_entry_panic
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endfunc tsp_cpu_on_entry
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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@ -305,6 +311,7 @@ tsp_cpu_on_entry_panic:
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func tsp_cpu_suspend_entry
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bl tsp_cpu_suspend_main
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restore_args_call_smc
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endfunc tsp_cpu_suspend_entry
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/*---------------------------------------------
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* This entrypoint is used by the TSPD to pass
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@ -357,6 +364,7 @@ func tsp_fiq_entry
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tsp_fiq_entry_panic:
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b tsp_fiq_entry_panic
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endfunc tsp_fiq_entry
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/*---------------------------------------------
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* This entrypoint is used by the TSPD when this
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@ -373,6 +381,7 @@ func tsp_cpu_resume_entry
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restore_args_call_smc
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tsp_cpu_resume_panic:
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b tsp_cpu_resume_panic
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endfunc tsp_cpu_resume_entry
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/*---------------------------------------------
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* This entrypoint is used by the TSPD to ask
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@ -384,6 +393,7 @@ func tsp_fast_smc_entry
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restore_args_call_smc
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tsp_fast_smc_entry_panic:
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b tsp_fast_smc_entry_panic
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endfunc tsp_fast_smc_entry
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/*---------------------------------------------
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* This entrypoint is used by the TSPD to ask
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@ -399,3 +409,4 @@ func tsp_std_smc_entry
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restore_args_call_smc
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tsp_std_smc_entry_panic:
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b tsp_std_smc_entry_panic
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endfunc tsp_std_smc_entry
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@ -56,6 +56,7 @@ func tsp_get_magic
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stp x0, x1, [x4, #0]
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ret
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endfunc tsp_get_magic
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.align 2
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_tsp_fid_get_magic:
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@ -98,6 +98,7 @@ func asm_assert
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asm_print_line_dec
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_assert_loop:
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b _assert_loop
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endfunc asm_assert
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#endif
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/*
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@ -114,6 +115,7 @@ func asm_print_str
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b 1b
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2:
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ret x3
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endfunc asm_print_str
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/*
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* This function prints a hexadecimal number in x4.
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@ -138,6 +140,7 @@ func asm_print_hex
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bl plat_crash_console_putc
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cbnz x5, 1b
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ret x3
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endfunc asm_print_hex
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/***********************************************************
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* The common implementation of do_panic for all BL stages
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@ -185,4 +188,5 @@ el3_panic:
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bl asm_print_hex
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_panic_loop:
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b _panic_loop
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endfunc do_panic
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@ -64,6 +64,7 @@ func console_init
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adrp x3, console_base
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str x0, [x3, :lo12:console_base]
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b console_core_init
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endfunc console_init
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/* -----------------------------------------------
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* int console_core_init(unsigned long base_addr,
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@ -107,6 +108,7 @@ func console_core_init
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mov w0, #1
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init_fail:
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ret
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endfunc console_core_init
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/* ---------------------------------------------
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* int console_putc(int c)
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@ -122,6 +124,7 @@ func console_putc
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adrp x2, console_base
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ldr x1, [x2, :lo12:console_base]
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b console_core_putc
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endfunc console_putc
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/* --------------------------------------------------------
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* int console_core_putc(int c, unsigned int base_addr)
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@ -154,6 +157,7 @@ func console_core_putc
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putc_error:
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mov w0, #-1
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ret
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endfunc console_core_putc
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/* ---------------------------------------------
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* int console_getc(void)
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@ -176,3 +180,4 @@ func console_getc
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getc_error:
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mov w0, #-1
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ret
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endfunc console_getc
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@ -85,9 +85,18 @@
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.macro func _name
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.section .text.\_name, "ax"
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.type \_name, %function
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.func \_name
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\_name:
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.endm
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/*
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* This macro is used to mark the end of a function.
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*/
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.macro endfunc _name
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.endfunc
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.size \_name, . - \_name
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.endm
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/* ---------------------------------------------
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* Find the type of reset and jump to handler
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* if present. If the handler is null then it is
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@ -56,6 +56,7 @@ flush_loop:
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b.lo flush_loop
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dsb sy
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ret
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endfunc flush_dcache_range
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/* ------------------------------------------
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@ -75,6 +76,7 @@ inv_loop:
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b.lo inv_loop
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dsb sy
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ret
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endfunc inv_dcache_range
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/* ---------------------------------------------------------------
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@ -154,6 +156,7 @@ level_done:
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isb
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exit:
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ret
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endfunc do_dcsw_op
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dcsw_loop_table:
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dcsw_loop isw
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@ -163,10 +166,12 @@ dcsw_loop_table:
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func dcsw_op_louis
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dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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endfunc dcsw_op_louis
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func dcsw_op_all
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dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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endfunc dcsw_op_all
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/* ---------------------------------------------------------------
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* Helper macro for data cache operations by set/way for the
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@ -189,6 +194,7 @@ func dcsw_op_all
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*/
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func dcsw_op_level1
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dcsw_op_level #(1 << LEVEL_SHIFT)
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endfunc dcsw_op_level1
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 2 cache
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@ -199,6 +205,7 @@ func dcsw_op_level1
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*/
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func dcsw_op_level2
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dcsw_op_level #(2 << LEVEL_SHIFT)
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endfunc dcsw_op_level2
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 3 cache
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@ -209,3 +216,4 @@ func dcsw_op_level2
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*/
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func dcsw_op_level3
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dcsw_op_level #(3 << LEVEL_SHIFT)
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endfunc dcsw_op_level3
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@ -53,6 +53,7 @@ func get_afflvl_shift
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mov x1, #MPIDR_AFFLVL_SHIFT
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lsl x0, x0, x1
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ret
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endfunc get_afflvl_shift
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func mpidr_mask_lower_afflvls
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cmp x1, #3
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@ -62,14 +63,17 @@ func mpidr_mask_lower_afflvls
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lsr x0, x0, x2
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lsl x0, x0, x2
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ret
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endfunc mpidr_mask_lower_afflvls
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func eret
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eret
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endfunc eret
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func smc
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smc #0
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endfunc smc
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/* -----------------------------------------------------------------------
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* void zeromem16(void *mem, unsigned int length);
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@ -97,7 +101,9 @@ z_loop1:
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b.eq z_end
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strb wzr, [x0], #1
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b z_loop1
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z_end: ret
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z_end:
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ret
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endfunc zeromem16
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/* --------------------------------------------------------------------------
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@ -129,7 +135,9 @@ m_loop1:
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strb w3, [x0], #1
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subs x2, x2, #1
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b.ne m_loop1
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m_end: ret
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m_end:
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ret
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endfunc memcpy16
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/* ---------------------------------------------------------------------------
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* Disable the MMU at EL3
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@ -148,11 +156,13 @@ do_disable_mmu:
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isb // ensure MMU is off
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mov x0, #DCCISW // DCache clean and invalidate
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b dcsw_op_all
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endfunc disable_mmu_el3
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func disable_mmu_icache_el3
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mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
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b do_disable_mmu
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endfunc disable_mmu_icache_el3
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/* ---------------------------------------------------------------------------
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* Enable the use of VFP at EL3
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@ -169,4 +179,5 @@ func enable_vfp
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msr cptr_el3, x0
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isb
|
||||
ret
|
||||
endfunc enable_vfp
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@ func aem_generic_core_pwr_dwn
|
|||
* ---------------------------------------------
|
||||
*/
|
||||
b dcsw_op_louis
|
||||
endfunc aem_generic_core_pwr_dwn
|
||||
|
||||
|
||||
func aem_generic_cluster_pwr_dwn
|
||||
|
|
@ -67,6 +68,7 @@ func aem_generic_cluster_pwr_dwn
|
|||
*/
|
||||
mov x0, #DCCISW
|
||||
b dcsw_op_all
|
||||
endfunc aem_generic_cluster_pwr_dwn
|
||||
|
||||
/* ---------------------------------------------
|
||||
* This function provides cpu specific
|
||||
|
|
@ -80,6 +82,7 @@ func aem_generic_cluster_pwr_dwn
|
|||
func aem_generic_cpu_reg_dump
|
||||
mov x6, #0 /* no registers to report */
|
||||
ret
|
||||
endfunc aem_generic_cpu_reg_dump
|
||||
|
||||
|
||||
/* cpu_ops for Base AEM FVP */
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@ func cortex_a53_disable_dcache
|
|||
msr sctlr_el3, x1
|
||||
isb
|
||||
ret
|
||||
endfunc cortex_a53_disable_dcache
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable intra-cluster coherency
|
||||
|
|
@ -56,6 +57,7 @@ func cortex_a53_disable_smp
|
|||
isb
|
||||
dsb sy
|
||||
ret
|
||||
endfunc cortex_a53_disable_smp
|
||||
|
||||
func cortex_a53_reset_func
|
||||
/* ---------------------------------------------
|
||||
|
|
@ -72,6 +74,7 @@ func cortex_a53_reset_func
|
|||
isb
|
||||
skip_smp_setup:
|
||||
ret
|
||||
endfunc cortex_a53_reset_func
|
||||
|
||||
func cortex_a53_core_pwr_dwn
|
||||
mov x18, x30
|
||||
|
|
@ -95,6 +98,7 @@ func cortex_a53_core_pwr_dwn
|
|||
*/
|
||||
mov x30, x18
|
||||
b cortex_a53_disable_smp
|
||||
endfunc cortex_a53_core_pwr_dwn
|
||||
|
||||
func cortex_a53_cluster_pwr_dwn
|
||||
mov x18, x30
|
||||
|
|
@ -131,6 +135,7 @@ func cortex_a53_cluster_pwr_dwn
|
|||
*/
|
||||
mov x30, x18
|
||||
b cortex_a53_disable_smp
|
||||
endfunc cortex_a53_cluster_pwr_dwn
|
||||
|
||||
/* ---------------------------------------------
|
||||
* This function provides cortex_a53 specific
|
||||
|
|
@ -149,5 +154,6 @@ func cortex_a53_cpu_reg_dump
|
|||
adr x6, cortex_a53_regs
|
||||
mrs x8, CPUECTLR_EL1
|
||||
ret
|
||||
endfunc cortex_a53_cpu_reg_dump
|
||||
|
||||
declare_cpu_ops cortex_a53, CORTEX_A53_MIDR
|
||||
|
|
|
|||
|
|
@ -45,6 +45,7 @@ func cortex_a57_disable_dcache
|
|||
msr sctlr_el3, x1
|
||||
isb
|
||||
ret
|
||||
endfunc cortex_a57_disable_dcache
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable all types of L2 prefetches.
|
||||
|
|
@ -60,6 +61,7 @@ func cortex_a57_disable_l2_prefetch
|
|||
isb
|
||||
dsb ish
|
||||
ret
|
||||
endfunc cortex_a57_disable_l2_prefetch
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable intra-cluster coherency
|
||||
|
|
@ -70,6 +72,7 @@ func cortex_a57_disable_smp
|
|||
bic x0, x0, #CPUECTLR_SMP_BIT
|
||||
msr CPUECTLR_EL1, x0
|
||||
ret
|
||||
endfunc cortex_a57_disable_smp
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable debug interfaces
|
||||
|
|
@ -81,6 +84,7 @@ func cortex_a57_disable_ext_debug
|
|||
isb
|
||||
dsb sy
|
||||
ret
|
||||
endfunc cortex_a57_disable_ext_debug
|
||||
|
||||
/* --------------------------------------------------
|
||||
* Errata Workaround for Cortex A57 Errata #806969.
|
||||
|
|
@ -113,6 +117,7 @@ apply_806969:
|
|||
msr CPUACTLR_EL1, x1
|
||||
skip_806969:
|
||||
ret
|
||||
endfunc errata_a57_806969_wa
|
||||
|
||||
|
||||
/* ---------------------------------------------------
|
||||
|
|
@ -146,6 +151,7 @@ apply_813420:
|
|||
msr CPUACTLR_EL1, x1
|
||||
skip_813420:
|
||||
ret
|
||||
endfunc errata_a57_813420_wa
|
||||
|
||||
/* -------------------------------------------------
|
||||
* The CPU Ops reset function for Cortex-A57.
|
||||
|
|
@ -188,6 +194,7 @@ func cortex_a57_reset_func
|
|||
skip_smp_setup:
|
||||
isb
|
||||
ret x19
|
||||
endfunc cortex_a57_reset_func
|
||||
|
||||
/* ----------------------------------------------------
|
||||
* The CPU Ops core power down function for Cortex-A57.
|
||||
|
|
@ -227,6 +234,7 @@ func cortex_a57_core_pwr_dwn
|
|||
*/
|
||||
mov x30, x18
|
||||
b cortex_a57_disable_ext_debug
|
||||
endfunc cortex_a57_core_pwr_dwn
|
||||
|
||||
/* -------------------------------------------------------
|
||||
* The CPU Ops cluster power down function for Cortex-A57.
|
||||
|
|
@ -280,6 +288,7 @@ func cortex_a57_cluster_pwr_dwn
|
|||
*/
|
||||
mov x30, x18
|
||||
b cortex_a57_disable_ext_debug
|
||||
endfunc cortex_a57_cluster_pwr_dwn
|
||||
|
||||
/* ---------------------------------------------
|
||||
* This function provides cortex_a57 specific
|
||||
|
|
@ -298,6 +307,7 @@ func cortex_a57_cpu_reg_dump
|
|||
adr x6, cortex_a57_regs
|
||||
mrs x8, CPUECTLR_EL1
|
||||
ret
|
||||
endfunc cortex_a57_cpu_reg_dump
|
||||
|
||||
|
||||
declare_cpu_ops cortex_a57, CORTEX_A57_MIDR
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@ func cortex_a72_disable_dcache
|
|||
msr sctlr_el3, x1
|
||||
isb
|
||||
ret
|
||||
endfunc cortex_a72_disable_dcache
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable all types of L2 prefetches.
|
||||
|
|
@ -58,6 +59,7 @@ func cortex_a72_disable_l2_prefetch
|
|||
msr CPUECTLR_EL1, x0
|
||||
isb
|
||||
ret
|
||||
endfunc cortex_a72_disable_l2_prefetch
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable the load-store hardware prefetcher.
|
||||
|
|
@ -70,6 +72,7 @@ func cortex_a72_disable_hw_prefetcher
|
|||
isb
|
||||
dsb ish
|
||||
ret
|
||||
endfunc cortex_a72_disable_hw_prefetcher
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable intra-cluster coherency
|
||||
|
|
@ -80,6 +83,7 @@ func cortex_a72_disable_smp
|
|||
bic x0, x0, #CPUECTLR_SMP_BIT
|
||||
msr CPUECTLR_EL1, x0
|
||||
ret
|
||||
endfunc cortex_a72_disable_smp
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Disable debug interfaces
|
||||
|
|
@ -91,6 +95,7 @@ func cortex_a72_disable_ext_debug
|
|||
isb
|
||||
dsb sy
|
||||
ret
|
||||
endfunc cortex_a72_disable_ext_debug
|
||||
|
||||
/* -------------------------------------------------
|
||||
* The CPU Ops reset function for Cortex-A72.
|
||||
|
|
@ -106,6 +111,7 @@ func cortex_a72_reset_func
|
|||
msr CPUECTLR_EL1, x0
|
||||
isb
|
||||
ret
|
||||
endfunc cortex_a72_reset_func
|
||||
|
||||
/* ----------------------------------------------------
|
||||
* The CPU Ops core power down function for Cortex-A72.
|
||||
|
|
@ -151,6 +157,7 @@ func cortex_a72_core_pwr_dwn
|
|||
*/
|
||||
mov x30, x18
|
||||
b cortex_a72_disable_ext_debug
|
||||
endfunc cortex_a72_core_pwr_dwn
|
||||
|
||||
/* -------------------------------------------------------
|
||||
* The CPU Ops cluster power down function for Cortex-A72.
|
||||
|
|
@ -211,6 +218,7 @@ func cortex_a72_cluster_pwr_dwn
|
|||
*/
|
||||
mov x30, x18
|
||||
b cortex_a72_disable_ext_debug
|
||||
endfunc cortex_a72_cluster_pwr_dwn
|
||||
|
||||
/* ---------------------------------------------
|
||||
* This function provides cortex_a72 specific
|
||||
|
|
@ -229,6 +237,7 @@ func cortex_a72_cpu_reg_dump
|
|||
adr x6, cortex_a72_regs
|
||||
mrs x8, CPUECTLR_EL1
|
||||
ret
|
||||
endfunc cortex_a72_cpu_reg_dump
|
||||
|
||||
|
||||
declare_cpu_ops cortex_a72, CORTEX_A72_MIDR
|
||||
|
|
|
|||
|
|
@ -67,6 +67,7 @@ func reset_handler
|
|||
br x2
|
||||
1:
|
||||
ret
|
||||
endfunc reset_handler
|
||||
|
||||
#endif /* IMAGE_BL1 || IMAGE_BL31 */
|
||||
|
||||
|
|
@ -88,6 +89,7 @@ func prepare_core_pwr_dwn
|
|||
/* Get the cpu_ops core_pwr_dwn handler */
|
||||
ldr x1, [x0, #CPU_PWR_DWN_CORE]
|
||||
br x1
|
||||
endfunc prepare_core_pwr_dwn
|
||||
|
||||
/*
|
||||
* The prepare cluster power down function for all platforms. After
|
||||
|
|
@ -106,6 +108,7 @@ func prepare_cluster_pwr_dwn
|
|||
/* Get the cpu_ops cluster_pwr_dwn handler */
|
||||
ldr x1, [x0, #CPU_PWR_DWN_CLUSTER]
|
||||
br x1
|
||||
endfunc prepare_cluster_pwr_dwn
|
||||
|
||||
|
||||
/*
|
||||
|
|
@ -129,6 +132,7 @@ func init_cpu_ops
|
|||
mov x30, x10
|
||||
1:
|
||||
ret
|
||||
endfunc init_cpu_ops
|
||||
#endif /* IMAGE_BL31 */
|
||||
|
||||
#if IMAGE_BL31 && CRASH_REPORTING
|
||||
|
|
@ -153,6 +157,7 @@ func do_cpu_reg_dump
|
|||
1:
|
||||
mov x30, x16
|
||||
ret
|
||||
endfunc do_cpu_reg_dump
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -197,6 +202,7 @@ func get_cpu_ops_ptr
|
|||
sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR)
|
||||
error_exit:
|
||||
ret
|
||||
endfunc get_cpu_ops_ptr
|
||||
|
||||
#if DEBUG
|
||||
/*
|
||||
|
|
@ -221,5 +227,6 @@ func print_revision_warning
|
|||
bl asm_print_str
|
||||
1:
|
||||
ret x5
|
||||
endfunc print_revision_warning
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -43,8 +43,10 @@ l2: ldaxr w1, [x0]
|
|||
stxr w1, w2, [x0]
|
||||
cbnz w1, l2
|
||||
ret
|
||||
endfunc spin_lock
|
||||
|
||||
|
||||
func spin_unlock
|
||||
stlr wzr, [x0]
|
||||
ret
|
||||
endfunc spin_unlock
|
||||
|
|
|
|||
|
|
@ -35,3 +35,4 @@
|
|||
func semihosting_call
|
||||
hlt #0xf000
|
||||
ret
|
||||
endfunc semihosting_call
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@ func platform_get_core_pos
|
|||
and x0, x0, #MPIDR_CLUSTER_MASK
|
||||
add x0, x1, x0, LSR #6
|
||||
ret
|
||||
endfunc platform_get_core_pos
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Placeholder function which should be redefined by
|
||||
|
|
@ -61,6 +62,7 @@ func platform_get_core_pos
|
|||
func platform_check_mpidr
|
||||
mov x0, xzr
|
||||
ret
|
||||
endfunc platform_check_mpidr
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Placeholder function which should be redefined by
|
||||
|
|
@ -69,6 +71,7 @@ func platform_check_mpidr
|
|||
*/
|
||||
func plat_report_exception
|
||||
ret
|
||||
endfunc plat_report_exception
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Placeholder function which should be redefined by
|
||||
|
|
@ -78,6 +81,7 @@ func plat_report_exception
|
|||
func plat_crash_console_init
|
||||
mov x0, #0
|
||||
ret
|
||||
endfunc plat_crash_console_init
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Placeholder function which should be redefined by
|
||||
|
|
@ -86,6 +90,7 @@ func plat_crash_console_init
|
|||
*/
|
||||
func plat_crash_console_putc
|
||||
ret
|
||||
endfunc plat_crash_console_putc
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Placeholder function which should be redefined by
|
||||
|
|
@ -94,6 +99,7 @@ func plat_crash_console_putc
|
|||
*/
|
||||
func plat_reset_handler
|
||||
ret
|
||||
endfunc plat_reset_handler
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Placeholder function which should be redefined by
|
||||
|
|
@ -103,3 +109,4 @@ func plat_reset_handler
|
|||
*/
|
||||
func plat_disable_acp
|
||||
ret
|
||||
endfunc plat_disable_acp
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@ func platform_get_stack
|
|||
mov x10, x30 // lr
|
||||
get_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE
|
||||
ret x10
|
||||
endfunc platform_get_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* void platform_set_stack (unsigned long mpidr)
|
||||
|
|
@ -62,6 +63,7 @@ func platform_set_stack
|
|||
bl platform_get_stack
|
||||
mov sp, x0
|
||||
ret x9
|
||||
endfunc platform_set_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Per-cpu stacks in normal memory. Each cpu gets a
|
||||
|
|
|
|||
|
|
@ -48,6 +48,7 @@
|
|||
func platform_get_stack
|
||||
get_up_stack platform_normal_stacks, PLATFORM_STACK_SIZE
|
||||
ret
|
||||
endfunc platform_get_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* void platform_set_stack (unsigned long)
|
||||
|
|
@ -61,6 +62,7 @@ func platform_set_stack
|
|||
get_up_stack platform_normal_stacks, PLATFORM_STACK_SIZE
|
||||
mov sp, x0
|
||||
ret
|
||||
endfunc platform_set_stack
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Single cpu stack in normal memory.
|
||||
|
|
|
|||
|
|
@ -97,6 +97,7 @@ func plat_secondary_cold_boot_setup
|
|||
wfi
|
||||
cb_panic:
|
||||
b cb_panic
|
||||
endfunc plat_secondary_cold_boot_setup
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
|
|
@ -148,6 +149,7 @@ warm_reset:
|
|||
exit:
|
||||
ret x9
|
||||
_panic: b _panic
|
||||
endfunc platform_get_entrypoint
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
|
|
@ -170,6 +172,7 @@ loop:
|
|||
subs w1, w1, #1
|
||||
b.gt loop
|
||||
ret
|
||||
endfunc platform_mem_init
|
||||
|
||||
/* ---------------------------------------------
|
||||
* void plat_report_exception(unsigned int type)
|
||||
|
|
@ -191,12 +194,14 @@ func plat_report_exception
|
|||
add x1, x1, #V2M_SYS_LED
|
||||
str w0, [x1]
|
||||
ret
|
||||
endfunc plat_report_exception
|
||||
|
||||
func platform_is_primary_cpu
|
||||
and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
|
||||
cmp x0, #FVP_PRIMARY_CPU
|
||||
cset x0, eq
|
||||
ret
|
||||
endfunc platform_is_primary_cpu
|
||||
|
||||
/* Define a crash console for the plaform */
|
||||
#define FVP_CRASH_CONSOLE_BASE PL011_UART1_BASE
|
||||
|
|
@ -213,6 +218,7 @@ func plat_crash_console_init
|
|||
mov_imm x1, PL011_UART1_CLK_IN_HZ
|
||||
mov_imm x2, PL011_BAUDRATE
|
||||
b console_core_init
|
||||
endfunc plat_crash_console_init
|
||||
|
||||
/* ---------------------------------------------
|
||||
* int plat_crash_console_putc(int c)
|
||||
|
|
@ -224,3 +230,4 @@ func plat_crash_console_init
|
|||
func plat_crash_console_putc
|
||||
mov_imm x1, FVP_CRASH_CONSOLE_BASE
|
||||
b console_core_putc
|
||||
endfunc plat_crash_console_putc
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@ func platform_is_primary_cpu
|
|||
cmp x0, x1
|
||||
cset x0, eq
|
||||
ret x9
|
||||
endfunc platform_is_primary_cpu
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* void plat_secondary_cold_boot_setup (void);
|
||||
|
|
@ -67,6 +68,7 @@ func plat_secondary_cold_boot_setup
|
|||
/* Juno todo: Implement secondary CPU cold boot setup on Juno */
|
||||
cb_panic:
|
||||
b cb_panic
|
||||
endfunc plat_secondary_cold_boot_setup
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
|
|
@ -91,6 +93,7 @@ func platform_get_entrypoint
|
|||
lsl x0, x0, #TRUSTED_MAILBOX_SHIFT
|
||||
ldr x0, [x1, x0]
|
||||
ret x9
|
||||
endfunc platform_get_entrypoint
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
|
|
@ -140,3 +143,4 @@ func platform_cold_boot_init
|
|||
|
||||
cb_init_panic:
|
||||
b cb_init_panic
|
||||
endfunc platform_cold_boot_init
|
||||
|
|
|
|||
|
|
@ -58,6 +58,7 @@ func plat_crash_console_init
|
|||
mov_imm x1, PL011_UART3_CLK_IN_HZ
|
||||
mov_imm x2, PL011_BAUDRATE
|
||||
b console_core_init
|
||||
endfunc plat_crash_console_init
|
||||
|
||||
/* ---------------------------------------------
|
||||
* int plat_crash_console_putc(int c)
|
||||
|
|
@ -69,6 +70,7 @@ func plat_crash_console_init
|
|||
func plat_crash_console_putc
|
||||
mov_imm x1, JUNO_CRASH_CONSOLE_BASE
|
||||
b console_core_putc
|
||||
endfunc plat_crash_console_putc
|
||||
|
||||
/* ---------------------------------------------
|
||||
* void plat_report_exception(unsigned int type)
|
||||
|
|
@ -90,6 +92,7 @@ func plat_report_exception
|
|||
add x1, x1, #V2M_SYS_LED
|
||||
str w0, [x1]
|
||||
ret
|
||||
endfunc plat_report_exception
|
||||
|
||||
/*
|
||||
* Return 0 to 3 for the A53s and 4 or 5 for the A57s
|
||||
|
|
@ -100,6 +103,7 @@ func platform_get_core_pos
|
|||
eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap A53/A57 order
|
||||
add x0, x1, x0, LSR #6
|
||||
ret
|
||||
endfunc platform_get_core_pos
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
|
|
@ -111,6 +115,7 @@ func platform_get_core_pos
|
|||
*/
|
||||
func platform_mem_init
|
||||
ret
|
||||
endfunc platform_mem_init
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* void plat_reset_handler(void);
|
||||
|
|
@ -197,3 +202,4 @@ ret:
|
|||
isb
|
||||
#endif /* FIRST_RESET_HANDLER_CALL */
|
||||
ret
|
||||
endfunc plat_reset_handler
|
||||
|
|
|
|||
|
|
@ -64,6 +64,7 @@ func opteed_enter_sp
|
|||
* ---------------------------------------------
|
||||
*/
|
||||
b el3_exit
|
||||
endfunc opteed_enter_sp
|
||||
|
||||
/* ---------------------------------------------
|
||||
* This function is called 'x0' pointing to a C
|
||||
|
|
@ -99,3 +100,4 @@ func opteed_exit_sp
|
|||
*/
|
||||
mov x0, x1
|
||||
ret
|
||||
endfunc opteed_exit_sp
|
||||
|
|
@ -66,6 +66,7 @@ func tlkd_enter_sp
|
|||
* ----------------------------------------------
|
||||
*/
|
||||
b el3_exit
|
||||
endfunc tlkd_enter_sp
|
||||
|
||||
/* ----------------------------------------------
|
||||
* This function is called with 'x0' pointing to
|
||||
|
|
@ -100,3 +101,4 @@ func tlkd_exit_sp
|
|||
*/
|
||||
mov x0, x1
|
||||
ret
|
||||
endfunc tlkd_exit_sp
|
||||
|
|
|
|||
|
|
@ -64,6 +64,7 @@ func tspd_enter_sp
|
|||
* ---------------------------------------------
|
||||
*/
|
||||
b el3_exit
|
||||
endfunc tspd_enter_sp
|
||||
|
||||
/* ---------------------------------------------
|
||||
* This function is called 'x0' pointing to a C
|
||||
|
|
@ -99,3 +100,4 @@ func tspd_exit_sp
|
|||
*/
|
||||
mov x0, x1
|
||||
ret
|
||||
endfunc tspd_exit_sp
|
||||
|
|
|
|||
|
|
@ -148,6 +148,7 @@ psci_aff_common_finish_entry:
|
|||
bl psci_afflvl_power_on_finish
|
||||
|
||||
b el3_exit
|
||||
endfunc psci_aff_on_finish_entry
|
||||
|
||||
/* --------------------------------------------
|
||||
* This function is called to indicate to the
|
||||
|
|
@ -163,4 +164,5 @@ func psci_power_down_wfi
|
|||
wfi
|
||||
wfi_spill:
|
||||
b wfi_spill
|
||||
endfunc psci_power_down_wfi
|
||||
|
||||
|
|
|
|||
|
|
@ -120,6 +120,7 @@ do_stack_maintenance:
|
|||
ldp x19, x20, [sp], #16
|
||||
ldp x29, x30, [sp], #16
|
||||
ret
|
||||
endfunc psci_do_pwrdown_cache_maintenance
|
||||
|
||||
|
||||
/* -----------------------------------------------------------------------
|
||||
|
|
@ -164,3 +165,4 @@ func psci_do_pwrup_cache_maintenance
|
|||
|
||||
ldp x29, x30, [sp], #16
|
||||
ret
|
||||
endfunc psci_do_pwrup_cache_maintenance
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue