mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-19 02:54:24 +00:00
8b779620d3
In order for the symbol table in the ELF file to contain the size of functions written in assembly, it is necessary to report it to the assembler using the .size directive. To fulfil the above requirements, this patch introduces an 'endfunc' macro which contains the .endfunc and .size directives. It also adds a .func directive to the 'func' assembler macro. The .func/.endfunc have been used so the assembler can fail if endfunc is omitted. Fixes ARM-Software/tf-issues#295 Change-Id: If8cb331b03d7f38fe7e3694d4de26f1075b278fc Signed-off-by: Kévin Petit <kevin.petit@arm.com>
206 lines
5.7 KiB
ArmAsm
206 lines
5.7 KiB
ArmAsm
/*
|
|
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are met:
|
|
*
|
|
* Redistributions of source code must retain the above copyright notice, this
|
|
* list of conditions and the following disclaimer.
|
|
*
|
|
* Redistributions in binary form must reproduce the above copyright notice,
|
|
* this list of conditions and the following disclaimer in the documentation
|
|
* and/or other materials provided with the distribution.
|
|
*
|
|
* Neither the name of ARM nor the names of its contributors may be used
|
|
* to endorse or promote products derived from this software without specific
|
|
* prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
|
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
* POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
#include <arch.h>
|
|
|
|
|
|
.macro func_prologue
|
|
stp x29, x30, [sp, #-0x10]!
|
|
mov x29,sp
|
|
.endm
|
|
|
|
.macro func_epilogue
|
|
ldp x29, x30, [sp], #0x10
|
|
.endm
|
|
|
|
|
|
.macro dcache_line_size reg, tmp
|
|
mrs \tmp, ctr_el0
|
|
ubfx \tmp, \tmp, #16, #4
|
|
mov \reg, #4
|
|
lsl \reg, \reg, \tmp
|
|
.endm
|
|
|
|
|
|
.macro icache_line_size reg, tmp
|
|
mrs \tmp, ctr_el0
|
|
and \tmp, \tmp, #0xf
|
|
mov \reg, #4
|
|
lsl \reg, \reg, \tmp
|
|
.endm
|
|
|
|
|
|
.macro smc_check label
|
|
mrs x0, esr_el3
|
|
ubfx x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
|
|
cmp x0, #EC_AARCH64_SMC
|
|
b.ne $label
|
|
.endm
|
|
|
|
|
|
/*
|
|
* This macro verifies that the a given vector doesn't exceed the
|
|
* architectural limit of 32 instructions. This is meant to be placed
|
|
* immedately after the last instruction in the vector. It takes the
|
|
* vector entry as the parameter
|
|
*/
|
|
.macro check_vector_size since
|
|
.if (. - \since) > (32 * 4)
|
|
.error "Vector exceeds 32 instructions"
|
|
.endif
|
|
.endm
|
|
|
|
/*
|
|
* This macro is used to create a function label and place the
|
|
* code into a separate text section based on the function name
|
|
* to enable elimination of unused code during linking
|
|
*/
|
|
.macro func _name
|
|
.section .text.\_name, "ax"
|
|
.type \_name, %function
|
|
.func \_name
|
|
\_name:
|
|
.endm
|
|
|
|
/*
|
|
* This macro is used to mark the end of a function.
|
|
*/
|
|
.macro endfunc _name
|
|
.endfunc
|
|
.size \_name, . - \_name
|
|
.endm
|
|
|
|
/* ---------------------------------------------
|
|
* Find the type of reset and jump to handler
|
|
* if present. If the handler is null then it is
|
|
* a cold boot. The primary cpu will set up the
|
|
* platform while the secondaries wait for
|
|
* their turn to be woken up
|
|
* ---------------------------------------------
|
|
*/
|
|
.macro wait_for_entrypoint
|
|
wait_for_entrypoint:
|
|
mrs x0, mpidr_el1
|
|
bl platform_get_entrypoint
|
|
cbnz x0, do_warm_boot
|
|
mrs x0, mpidr_el1
|
|
bl platform_is_primary_cpu
|
|
cbnz x0, do_cold_boot
|
|
|
|
/* ---------------------------------------------
|
|
* Perform any platform specific secondary cpu
|
|
* actions
|
|
* ---------------------------------------------
|
|
*/
|
|
bl plat_secondary_cold_boot_setup
|
|
b wait_for_entrypoint
|
|
|
|
do_warm_boot:
|
|
/* ---------------------------------------------
|
|
* Jump to BL31 for all warm boot init.
|
|
* ---------------------------------------------
|
|
*/
|
|
blr x0
|
|
|
|
do_cold_boot:
|
|
.endm
|
|
|
|
/*
|
|
* This macro declares an array of 1 or more stacks, properly
|
|
* aligned and in the requested section
|
|
*/
|
|
#define STACK_ALIGN 6
|
|
|
|
.macro declare_stack _name, _section, _size, _count
|
|
.if ((\_size & ((1 << STACK_ALIGN) - 1)) <> 0)
|
|
.error "Stack size not correctly aligned"
|
|
.endif
|
|
.section \_section, "aw", %nobits
|
|
.align STACK_ALIGN
|
|
\_name:
|
|
.space ((\_count) * (\_size)), 0
|
|
.endm
|
|
|
|
/*
|
|
* This macro calculates the base address of an MP stack using the
|
|
* platform_get_core_pos() index, the name of the stack storage and
|
|
* the size of each stack
|
|
* In: X0 = MPIDR of CPU whose stack is wanted
|
|
* Out: X0 = physical address of stack base
|
|
* Clobber: X30, X1, X2
|
|
*/
|
|
.macro get_mp_stack _name, _size
|
|
bl platform_get_core_pos
|
|
ldr x2, =(\_name + \_size)
|
|
mov x1, #\_size
|
|
madd x0, x0, x1, x2
|
|
.endm
|
|
|
|
/*
|
|
* This macro calculates the base address of a UP stack using the
|
|
* name of the stack storage and the size of the stack
|
|
* Out: X0 = physical address of stack base
|
|
*/
|
|
.macro get_up_stack _name, _size
|
|
ldr x0, =(\_name + \_size)
|
|
.endm
|
|
|
|
/*
|
|
* Helper macro to generate the best mov/movk combinations according
|
|
* the value to be moved. The 16 bits from '_shift' are tested and
|
|
* if not zero, they are moved into '_reg' without affecting
|
|
* other bits.
|
|
*/
|
|
.macro _mov_imm16 _reg, _val, _shift
|
|
.if (\_val >> \_shift) & 0xffff
|
|
.if (\_val & (1 << \_shift - 1))
|
|
movk \_reg, (\_val >> \_shift) & 0xffff, LSL \_shift
|
|
.else
|
|
mov \_reg, \_val & (0xffff << \_shift)
|
|
.endif
|
|
.endif
|
|
.endm
|
|
|
|
/*
|
|
* Helper macro to load arbitrary values into 32 or 64-bit registers
|
|
* which generates the best mov/movk combinations. Many base addresses
|
|
* are 64KB aligned the macro will eliminate updating bits 15:0 in
|
|
* that case
|
|
*/
|
|
.macro mov_imm _reg, _val
|
|
.if (\_val) == 0
|
|
mov \_reg, #0
|
|
.else
|
|
_mov_imm16 \_reg, (\_val), 0
|
|
_mov_imm16 \_reg, (\_val), 16
|
|
_mov_imm16 \_reg, (\_val), 32
|
|
_mov_imm16 \_reg, (\_val), 48
|
|
.endif
|
|
.endm
|