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https://github.com/ARM-software/arm-trusted-firmware.git
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8b779620d3
In order for the symbol table in the ELF file to contain the size of functions written in assembly, it is necessary to report it to the assembler using the .size directive. To fulfil the above requirements, this patch introduces an 'endfunc' macro which contains the .endfunc and .size directives. It also adds a .func directive to the 'func' assembler macro. The .func/.endfunc have been used so the assembler can fail if endfunc is omitted. Fixes ARM-Software/tf-issues#295 Change-Id: If8cb331b03d7f38fe7e3694d4de26f1075b278fc Signed-off-by: Kévin Petit <kevin.petit@arm.com>
305 lines
8.2 KiB
ArmAsm
305 lines
8.2 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <context.h>
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/* -----------------------------------------------------
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* The following function strictly follows the AArch64
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* PCS to use x9-x17 (temporary caller-saved registers)
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* to save EL1 system register context. It assumes that
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* 'x0' is pointing to a 'el1_sys_regs' structure where
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* the register context will be saved.
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* -----------------------------------------------------
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*/
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.global el1_sysregs_context_save
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func el1_sysregs_context_save
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mrs x9, spsr_el1
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mrs x10, elr_el1
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stp x9, x10, [x0, #CTX_SPSR_EL1]
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mrs x11, spsr_abt
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mrs x12, spsr_und
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stp x11, x12, [x0, #CTX_SPSR_ABT]
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mrs x13, spsr_irq
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mrs x14, spsr_fiq
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stp x13, x14, [x0, #CTX_SPSR_IRQ]
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mrs x15, sctlr_el1
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mrs x16, actlr_el1
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stp x15, x16, [x0, #CTX_SCTLR_EL1]
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mrs x17, cpacr_el1
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mrs x9, csselr_el1
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stp x17, x9, [x0, #CTX_CPACR_EL1]
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mrs x10, sp_el1
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mrs x11, esr_el1
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stp x10, x11, [x0, #CTX_SP_EL1]
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mrs x12, ttbr0_el1
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mrs x13, ttbr1_el1
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stp x12, x13, [x0, #CTX_TTBR0_EL1]
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mrs x14, mair_el1
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mrs x15, amair_el1
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stp x14, x15, [x0, #CTX_MAIR_EL1]
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mrs x16, tcr_el1
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mrs x17, tpidr_el1
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stp x16, x17, [x0, #CTX_TCR_EL1]
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mrs x9, tpidr_el0
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mrs x10, tpidrro_el0
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stp x9, x10, [x0, #CTX_TPIDR_EL0]
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mrs x11, dacr32_el2
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mrs x12, ifsr32_el2
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stp x11, x12, [x0, #CTX_DACR32_EL2]
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mrs x13, par_el1
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mrs x14, far_el1
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stp x13, x14, [x0, #CTX_PAR_EL1]
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mrs x15, afsr0_el1
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mrs x16, afsr1_el1
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stp x15, x16, [x0, #CTX_AFSR0_EL1]
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mrs x17, contextidr_el1
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mrs x9, vbar_el1
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stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1]
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/* Save NS timer registers if the build has instructed so */
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#if NS_TIMER_SWITCH
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mrs x10, cntp_ctl_el0
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mrs x11, cntp_cval_el0
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stp x10, x11, [x0, #CTX_CNTP_CTL_EL0]
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mrs x12, cntv_ctl_el0
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mrs x13, cntv_cval_el0
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stp x12, x13, [x0, #CTX_CNTV_CTL_EL0]
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mrs x14, cntkctl_el1
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str x14, [x0, #CTX_CNTKCTL_EL1]
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#endif
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mrs x15, fpexc32_el2
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str x15, [x0, #CTX_FP_FPEXC32_EL2]
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ret
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endfunc el1_sysregs_context_save
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/* -----------------------------------------------------
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* The following function strictly follows the AArch64
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* PCS to use x9-x17 (temporary caller-saved registers)
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* to restore EL1 system register context. It assumes
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* that 'x0' is pointing to a 'el1_sys_regs' structure
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* from where the register context will be restored
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* -----------------------------------------------------
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*/
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.global el1_sysregs_context_restore
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func el1_sysregs_context_restore
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ldp x9, x10, [x0, #CTX_SPSR_EL1]
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msr spsr_el1, x9
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msr elr_el1, x10
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ldp x11, x12, [x0, #CTX_SPSR_ABT]
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msr spsr_abt, x11
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msr spsr_und, x12
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ldp x13, x14, [x0, #CTX_SPSR_IRQ]
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msr spsr_irq, x13
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msr spsr_fiq, x14
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ldp x15, x16, [x0, #CTX_SCTLR_EL1]
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msr sctlr_el1, x15
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msr actlr_el1, x16
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ldp x17, x9, [x0, #CTX_CPACR_EL1]
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msr cpacr_el1, x17
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msr csselr_el1, x9
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ldp x10, x11, [x0, #CTX_SP_EL1]
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msr sp_el1, x10
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msr esr_el1, x11
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ldp x12, x13, [x0, #CTX_TTBR0_EL1]
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msr ttbr0_el1, x12
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msr ttbr1_el1, x13
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ldp x14, x15, [x0, #CTX_MAIR_EL1]
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msr mair_el1, x14
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msr amair_el1, x15
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ldp x16, x17, [x0, #CTX_TCR_EL1]
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msr tcr_el1, x16
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msr tpidr_el1, x17
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ldp x9, x10, [x0, #CTX_TPIDR_EL0]
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msr tpidr_el0, x9
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msr tpidrro_el0, x10
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ldp x11, x12, [x0, #CTX_DACR32_EL2]
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msr dacr32_el2, x11
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msr ifsr32_el2, x12
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ldp x13, x14, [x0, #CTX_PAR_EL1]
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msr par_el1, x13
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msr far_el1, x14
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ldp x15, x16, [x0, #CTX_AFSR0_EL1]
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msr afsr0_el1, x15
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msr afsr1_el1, x16
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ldp x17, x9, [x0, #CTX_CONTEXTIDR_EL1]
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msr contextidr_el1, x17
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msr vbar_el1, x9
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/* Restore NS timer registers if the build has instructed so */
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#if NS_TIMER_SWITCH
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ldp x10, x11, [x0, #CTX_CNTP_CTL_EL0]
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msr cntp_ctl_el0, x10
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msr cntp_cval_el0, x11
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ldp x12, x13, [x0, #CTX_CNTV_CTL_EL0]
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msr cntv_ctl_el0, x12
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msr cntv_cval_el0, x13
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ldr x14, [x0, #CTX_CNTKCTL_EL1]
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msr cntkctl_el1, x14
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#endif
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ldr x15, [x0, #CTX_FP_FPEXC32_EL2]
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msr fpexc32_el2, x15
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/* No explict ISB required here as ERET covers it */
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ret
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endfunc el1_sysregs_context_restore
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/* -----------------------------------------------------
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* The following function follows the aapcs_64 strictly
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* to use x9-x17 (temporary caller-saved registers
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* according to AArch64 PCS) to save floating point
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* register context. It assumes that 'x0' is pointing to
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* a 'fp_regs' structure where the register context will
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* be saved.
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*
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* Access to VFP registers will trap if CPTR_EL3.TFP is
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* set. However currently we don't use VFP registers
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* nor set traps in Trusted Firmware, and assume it's
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* cleared
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*
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* TODO: Revisit when VFP is used in secure world
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* -----------------------------------------------------
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*/
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#if CTX_INCLUDE_FPREGS
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.global fpregs_context_save
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func fpregs_context_save
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stp q0, q1, [x0, #CTX_FP_Q0]
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stp q2, q3, [x0, #CTX_FP_Q2]
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stp q4, q5, [x0, #CTX_FP_Q4]
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stp q6, q7, [x0, #CTX_FP_Q6]
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stp q8, q9, [x0, #CTX_FP_Q8]
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stp q10, q11, [x0, #CTX_FP_Q10]
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stp q12, q13, [x0, #CTX_FP_Q12]
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stp q14, q15, [x0, #CTX_FP_Q14]
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stp q16, q17, [x0, #CTX_FP_Q16]
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stp q18, q19, [x0, #CTX_FP_Q18]
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stp q20, q21, [x0, #CTX_FP_Q20]
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stp q22, q23, [x0, #CTX_FP_Q22]
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stp q24, q25, [x0, #CTX_FP_Q24]
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stp q26, q27, [x0, #CTX_FP_Q26]
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stp q28, q29, [x0, #CTX_FP_Q28]
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stp q30, q31, [x0, #CTX_FP_Q30]
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mrs x9, fpsr
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str x9, [x0, #CTX_FP_FPSR]
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mrs x10, fpcr
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str x10, [x0, #CTX_FP_FPCR]
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ret
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endfunc fpregs_context_save
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/* -----------------------------------------------------
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* The following function follows the aapcs_64 strictly
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* to use x9-x17 (temporary caller-saved registers
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* according to AArch64 PCS) to restore floating point
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* register context. It assumes that 'x0' is pointing to
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* a 'fp_regs' structure from where the register context
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* will be restored.
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*
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* Access to VFP registers will trap if CPTR_EL3.TFP is
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* set. However currently we don't use VFP registers
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* nor set traps in Trusted Firmware, and assume it's
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* cleared
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*
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* TODO: Revisit when VFP is used in secure world
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* -----------------------------------------------------
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*/
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.global fpregs_context_restore
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func fpregs_context_restore
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ldp q0, q1, [x0, #CTX_FP_Q0]
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ldp q2, q3, [x0, #CTX_FP_Q2]
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ldp q4, q5, [x0, #CTX_FP_Q4]
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ldp q6, q7, [x0, #CTX_FP_Q6]
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ldp q8, q9, [x0, #CTX_FP_Q8]
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ldp q10, q11, [x0, #CTX_FP_Q10]
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ldp q12, q13, [x0, #CTX_FP_Q12]
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ldp q14, q15, [x0, #CTX_FP_Q14]
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ldp q16, q17, [x0, #CTX_FP_Q16]
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ldp q18, q19, [x0, #CTX_FP_Q18]
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ldp q20, q21, [x0, #CTX_FP_Q20]
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ldp q22, q23, [x0, #CTX_FP_Q22]
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ldp q24, q25, [x0, #CTX_FP_Q24]
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ldp q26, q27, [x0, #CTX_FP_Q26]
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ldp q28, q29, [x0, #CTX_FP_Q28]
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ldp q30, q31, [x0, #CTX_FP_Q30]
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ldr x9, [x0, #CTX_FP_FPSR]
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msr fpsr, x9
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str x10, [x0, #CTX_FP_FPCR]
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msr fpcr, x10
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/*
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* No explict ISB required here as ERET to
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* swtich to secure EL1 or non-secure world
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* covers it
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*/
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ret
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endfunc fpregs_context_restore
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#endif /* CTX_INCLUDE_FPREGS */
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