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Rename Cortex-Hercules to Cortex-A78
Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
This commit is contained in:
Jimmy Brisson
parent
83c1584dcb
commit
3f35709c55
5 changed files with 66 additions and 67 deletions
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@ -227,11 +227,10 @@ For Cortex-A76, the following errata build flags are defined :
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- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
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CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
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For Hercules, the following errata build flags are defined :
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For Cortex-A78, the following errata build flags are defined :
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- ``ERRATA_HERCULES_1688305``: This applies errata 1688305 workaround to
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Hercules CPU. This needs to be enabled only for revision r0p0 - r1p0 of
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the CPU.
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- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
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CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
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For Neoverse N1, the following errata build flags are defined :
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@ -338,7 +337,7 @@ architecture that can be enabled by the platform as desired.
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--------------
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*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*
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*Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.*
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.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
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.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
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@ -4,31 +4,31 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_HERCULES_H
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#define CORTEX_HERCULES_H
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#ifndef CORTEX_A78_H
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#define CORTEX_A78_H
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#include <lib/utils_def.h>
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#define CORTEX_HERCULES_MIDR U(0x410FD410)
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#define CORTEX_A78_MIDR U(0x410FD410)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_HERCULES_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_HERCULES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
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#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30)
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#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
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#define CORTEX_HERCULES_ACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_HERCULES_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
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#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
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/*******************************************************************************
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* CPU Activity Monitor Unit register specific definitions.
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@ -38,7 +38,7 @@
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#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
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#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
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#define CORTEX_HERCULES_AMU_GROUP0_MASK U(0xF)
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#define CORTEX_HERCULES_AMU_GROUP1_MASK U(0x7)
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#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
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#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
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#endif /* CORTEX_HERCULES_H */
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#endif /* CORTEX_A78_H */
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@ -13,30 +13,30 @@
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled"
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#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Hercules Erratum 1688305.
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* This applies to revision r0p0 and r1p0 of Hercules.
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* Errata Workaround for A78 Erratum 1688305.
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* This applies to revision r0p0 and r1p0 of A78.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_hercules_1688305_wa
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func errata_a78_1688305_wa
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/* Compare x0 against revision r1p0 */
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mov x17, x30
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bl check_errata_1688305
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cbz x0, 1f
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mrs x1, CORTEX_HERCULES_ACTLR2_EL1
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orr x1, x1, CORTEX_HERCULES_ACTLR2_EL1_BIT_1
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msr CORTEX_HERCULES_ACTLR2_EL1, x1
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mrs x1, CORTEX_A78_ACTLR2_EL1
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orr x1, x1, CORTEX_A78_ACTLR2_EL1_BIT_1
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msr CORTEX_A78_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_hercules_1688305_wa
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endfunc errata_a78_1688305_wa
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func check_errata_1688305
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/* Applies to r0p0 and r1p0 */
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@ -45,64 +45,64 @@ func check_errata_1688305
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endfunc check_errata_1688305
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-Hercules
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* The CPU Ops reset function for Cortex-A78
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* -------------------------------------------------
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*/
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func cortex_hercules_reset_func
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func cortex_a78_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_HERCULES_1688305
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#if ERRATA_A78_1688305
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mov x0, x18
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bl errata_hercules_1688305_wa
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bl errata_a78_1688305_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
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bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
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msr actlr_el3, x0
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/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
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bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
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msr actlr_el2, x0
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/* Enable group0 counters */
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mov x0, #CORTEX_HERCULES_AMU_GROUP0_MASK
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mov x0, #CORTEX_A78_AMU_GROUP0_MASK
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msr CPUAMCNTENSET0_EL0, x0
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/* Enable group1 counters */
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mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK
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mov x0, #CORTEX_A78_AMU_GROUP1_MASK
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msr CPUAMCNTENSET1_EL0, x0
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#endif
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isb
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ret x19
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endfunc cortex_hercules_reset_func
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endfunc cortex_a78_reset_func
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_hercules_core_pwr_dwn
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func cortex_a78_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_HERCULES_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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msr CORTEX_HERCULES_CPUPWRCTLR_EL1, x0
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mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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msr CORTEX_A78_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_hercules_core_pwr_dwn
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endfunc cortex_a78_core_pwr_dwn
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/*
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* Errata printing function for cortex_hercules. Must follow AAPCS.
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* Errata printing function for cortex_a78. Must follow AAPCS.
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*/
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#if REPORT_ERRATA
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func cortex_hercules_errata_report
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func cortex_a78_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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@ -112,15 +112,15 @@ func cortex_hercules_errata_report
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_HERCULES_1688305, cortex_hercules, 1688305
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report_errata ERRATA_A78_1688305, cortex_a78, 1688305
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_hercules_errata_report
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endfunc cortex_a78_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cortex_hercules specific
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* This function provides cortex_a78 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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@ -128,16 +128,16 @@ endfunc cortex_hercules_errata_report
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_hercules_regs, "aS"
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cortex_hercules_regs: /* The ascii list of register names to be reported */
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.section .rodata.cortex_a78_regs, "aS"
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cortex_a78_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_hercules_cpu_reg_dump
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adr x6, cortex_hercules_regs
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mrs x8, CORTEX_HERCULES_CPUECTLR_EL1
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func cortex_a78_cpu_reg_dump
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adr x6, cortex_a78_regs
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mrs x8, CORTEX_A78_CPUECTLR_EL1
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ret
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endfunc cortex_hercules_cpu_reg_dump
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endfunc cortex_a78_cpu_reg_dump
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declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \
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cortex_hercules_reset_func, \
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cortex_hercules_core_pwr_dwn
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declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \
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cortex_a78_reset_func, \
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cortex_a78_core_pwr_dwn
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, ARM Limited. All rights reserved.
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -24,20 +24,20 @@
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func cortex_hercules_ae_reset_func
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
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bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
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msr actlr_el3, x0
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/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
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bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
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msr actlr_el2, x0
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/* Enable group0 counters */
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mov x0, #CORTEX_HERCULES_AMU_GROUP0_MASK
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mov x0, #CORTEX_A78_AMU_GROUP0_MASK
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msr CPUAMCNTENSET0_EL0, x0
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/* Enable group1 counters */
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mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK
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mov x0, #CORTEX_A78_AMU_GROUP1_MASK
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msr CPUAMCNTENSET1_EL0, x0
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isb
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@ -54,9 +54,9 @@ func cortex_hercules_ae_core_pwr_dwn
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* Enable CPU power down bit in power control register
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* -------------------------------------------------------
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*/
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mrs x0, CORTEX_HERCULES_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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msr CORTEX_HERCULES_CPUPWRCTLR_EL1, x0
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mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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msr CORTEX_A78_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_hercules_ae_core_pwr_dwn
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@ -85,7 +85,7 @@ cortex_hercules_ae_regs: /* The ascii list of register names to be reported */
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func cortex_hercules_ae_cpu_reg_dump
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adr x6, cortex_hercules_ae_regs
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mrs x8, CORTEX_HERCULES_CPUECTLR_EL1
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mrs x8, CORTEX_A78_CPUECTLR_EL1
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ret
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endfunc cortex_hercules_ae_cpu_reg_dump
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@ -251,8 +251,8 @@ ERRATA_A76_1275112 ?=0
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ERRATA_A76_1286807 ?=0
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# Flag to apply erratum 1688305 workaround during reset. This erratum applies
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# to revisions r0p0 - r1p0 of the Hercules cpu.
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ERRATA_HERCULES_1688305 ?=0
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# to revisions r0p0 - r1p0 of the A78 cpu.
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ERRATA_A78_1688305 ?=0
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# Flag to apply T32 CLREX workaround during reset. This erratum applies
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# only to r0p0 and r1p0 of the Neoverse N1 cpu.
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@ -487,9 +487,9 @@ $(eval $(call add_define,ERRATA_A76_1275112))
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$(eval $(call assert_boolean,ERRATA_A76_1286807))
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$(eval $(call add_define,ERRATA_A76_1286807))
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# Process ERRATA_HERCULES_1688305 flag
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$(eval $(call assert_boolean,ERRATA_HERCULES_1688305))
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$(eval $(call add_define,ERRATA_HERCULES_1688305))
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# Process ERRATA_A78_1688305 flag
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$(eval $(call assert_boolean,ERRATA_A78_1688305))
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$(eval $(call add_define,ERRATA_A78_1688305))
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# Process ERRATA_N1_1043202 flag
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$(eval $(call assert_boolean,ERRATA_N1_1043202))
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