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3f35709c55
Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
44 lines
1.7 KiB
C
44 lines
1.7 KiB
C
/*
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A78_H
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#define CORTEX_A78_H
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#include <lib/utils_def.h>
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#define CORTEX_A78_MIDR U(0x410FD410)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
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#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
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/*******************************************************************************
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* CPU Activity Monitor Unit register specific definitions.
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******************************************************************************/
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#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
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#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
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#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
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#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
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#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
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#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
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#endif /* CORTEX_A78_H */
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