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https://github.com/ARM-software/arm-trusted-firmware.git
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3f35709c55
Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
143 lines
3.5 KiB
ArmAsm
143 lines
3.5 KiB
ArmAsm
/*
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a78.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for A78 Erratum 1688305.
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* This applies to revision r0p0 and r1p0 of A78.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_1688305_wa
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/* Compare x0 against revision r1p0 */
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mov x17, x30
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bl check_errata_1688305
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cbz x0, 1f
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mrs x1, CORTEX_A78_ACTLR2_EL1
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orr x1, x1, CORTEX_A78_ACTLR2_EL1_BIT_1
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msr CORTEX_A78_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a78_1688305_wa
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func check_errata_1688305
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1688305
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A78
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* -------------------------------------------------
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*/
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func cortex_a78_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A78_1688305
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mov x0, x18
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bl errata_a78_1688305_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
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msr actlr_el3, x0
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/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
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msr actlr_el2, x0
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/* Enable group0 counters */
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mov x0, #CORTEX_A78_AMU_GROUP0_MASK
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msr CPUAMCNTENSET0_EL0, x0
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/* Enable group1 counters */
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mov x0, #CORTEX_A78_AMU_GROUP1_MASK
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msr CPUAMCNTENSET1_EL0, x0
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#endif
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isb
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ret x19
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endfunc cortex_a78_reset_func
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_a78_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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msr CORTEX_A78_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a78_core_pwr_dwn
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/*
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* Errata printing function for cortex_a78. Must follow AAPCS.
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*/
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#if REPORT_ERRATA
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func cortex_a78_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A78_1688305, cortex_a78, 1688305
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a78_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cortex_a78 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a78_regs, "aS"
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cortex_a78_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a78_cpu_reg_dump
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adr x6, cortex_a78_regs
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mrs x8, CORTEX_A78_CPUECTLR_EL1
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ret
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endfunc cortex_a78_cpu_reg_dump
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declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \
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cortex_a78_reset_func, \
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cortex_a78_core_pwr_dwn
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