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fix(cpus): workaround for Cortex-X4 erratum 2816013

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Cortex-X4 erratum 2816013 is a Cat B erratum that applies
to all revisions <= r0p1 and is fixed in r0p2. This erratum
is only present when memory tagging is enabled.

The workaround is to set CPUACTLR5_EL1[14] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest

Change-Id: I546044bde6e5eedd0abf61643d25e2dd2036df5c
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
This commit is contained in:
Sona Mathew 2024-07-16 14:34:42 -05:00
parent 66f6d3bf8f
commit 1e4480bb54
4 changed files with 23 additions and 0 deletions
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3
docs/design/cpu-specific-build-macros.rst
View file

@ -833,6 +833,9 @@ For Cortex-X4, the following errata build flags are defined :
- ``ERRATA_X4_2763018``: This applies errata 2763018 workaround to Cortex-X4
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
- ``ERRATA_X4_2816013``: This applies errata 2816013 workaround to Cortex-X4
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
For Cortex-A510, the following errata build flags are defined :
- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to

6
include/lib/cpus/aarch64/cortex_x4.h
View file

@ -28,4 +28,10 @@
******************************************************************************/
#define CORTEX_X4_CPUACTLR3_EL1 S3_0_C15_C1_2
/*******************************************************************************
* CPU Auxiliary control register 5 specific definitions
******************************************************************************/
#define CORTEX_X4_CPUACTLR5_EL1 S3_0_C15_C8_0
#define CORTEX_X4_CPUACTLR5_EL1_BIT_14 (ULL(1) << 14)
#endif /* CORTEX_X4_H */

10
lib/cpus/aarch64/cortex_x4.S
View file

@ -39,6 +39,16 @@ workaround_reset_end cortex_x4, ERRATUM(2763018)
check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1)
workaround_reset_start cortex_x4, ERRATUM(2816013), ERRATA_X4_2816013
mrs x1, id_aa64pfr1_el1
ubfx x2, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4
cbz x2, #1f
sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14)
1:
workaround_reset_end cortex_x4, ERRATUM(2816013)
check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1)
workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*

4
lib/cpus/cpu-ops.mk
View file

@ -831,6 +831,10 @@ CPU_FLAG_LIST += ERRATA_X4_2740089
# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_X4_2763018
# Flag to apply erratum 2816013 workaround on reset. This erratum applies
# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_X4_2816013
# Flag to apply erratum 1922240 workaround during reset. This erratum applies
# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A510_1922240