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1e4480bb54
Cortex-X4 erratum 2816013 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2. This erratum is only present when memory tagging is enabled. The workaround is to set CPUACTLR5_EL1[14] to 1. SDEN documentation: https://developer.arm.com/documentation/SDEN-2432808/latest Change-Id: I546044bde6e5eedd0abf61643d25e2dd2036df5c Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
109 lines
3.3 KiB
ArmAsm
109 lines
3.3 KiB
ArmAsm
/*
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* Copyright (c) 2022-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_x4.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4
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#endif /* WORKAROUND_CVE_2022_23960 */
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workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end cortex_x4, ERRATUM(2740089)
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check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018
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sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(47)
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workaround_reset_end cortex_x4, ERRATUM(2763018)
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check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, ERRATUM(2816013), ERRATA_X4_2816013
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mrs x1, id_aa64pfr1_el1
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ubfx x2, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4
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cbz x2, #1f
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sysreg_bit_set CORTEX_X4_CPUACTLR5_EL1, BIT(14)
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1:
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workaround_reset_end cortex_x4, ERRATUM(2816013)
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check_erratum_ls cortex_x4, ERRATUM(2816013), CPU_REV(0, 1)
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workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex X4 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_cortex_x4
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_x4, CVE(2022, 23960)
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check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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cpu_reset_func_start cortex_x4
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end cortex_x4
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_x4_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
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isb
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ret
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endfunc cortex_x4_core_pwr_dwn
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errata_report_shim cortex_x4
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/* ---------------------------------------------
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* This function provides Cortex X4-specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_x4_regs, "aS"
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cortex_x4_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_x4_cpu_reg_dump
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adr x6, cortex_x4_regs
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mrs x8, CORTEX_X4_CPUECTLR_EL1
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ret
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endfunc cortex_x4_cpu_reg_dump
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declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \
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cortex_x4_reset_func, \
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cortex_x4_core_pwr_dwn
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