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1e4480bb54
Cortex-X4 erratum 2816013 is a Cat B erratum that applies to all revisions <= r0p1 and is fixed in r0p2. This erratum is only present when memory tagging is enabled. The workaround is to set CPUACTLR5_EL1[14] to 1. SDEN documentation: https://developer.arm.com/documentation/SDEN-2432808/latest Change-Id: I546044bde6e5eedd0abf61643d25e2dd2036df5c Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
37 lines
1.5 KiB
C
37 lines
1.5 KiB
C
/*
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* Copyright (c) 2022-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_X4_H
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#define CORTEX_X4_H
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#define CORTEX_X4_MIDR U(0x410FD821)
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/* Cortex X4 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_X4_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary control register specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUACTLR3_EL1 S3_0_C15_C1_2
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/*******************************************************************************
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* CPU Auxiliary control register 5 specific definitions
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******************************************************************************/
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#define CORTEX_X4_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define CORTEX_X4_CPUACTLR5_EL1_BIT_14 (ULL(1) << 14)
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#endif /* CORTEX_X4_H */
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