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fix(cpus): workaround for Cortex-A720 erratum 2844092

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Cortex-A720 erratum 2844092 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set bit[11] of CPUACTLR4_EL1 register.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2439421/latest

Change-Id: I3d8eacb26cba42774f1f31c3aae2a0e6fecec614
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
This commit is contained in:
Sona Mathew 2024-07-19 18:09:20 -05:00
parent 1e4480bb54
commit 12140908a5
4 changed files with 19 additions and 0 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -932,6 +932,10 @@ For Cortex-A715, the following errata build flags are defined :
For Cortex-A720, the following errata build flags are defined :
- ``ERRATA_A720_2844092``: This applies errata 2844092 workaround to
Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
It is fixed in r0p2.
- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to
Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
It is fixed in r0p2.

5
include/lib/cpus/aarch64/cortex_a720.h
View file

@ -22,6 +22,11 @@
******************************************************************************/
#define CORTEX_A720_CPUACTLR2_EL1 S3_0_C15_C1_1
/*******************************************************************************
* CPU Auxiliary Control register 4 specific definitions.
******************************************************************************/
#define CORTEX_A720_CPUACTLR4_EL1 S3_0_C15_C1_3
/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/

6
lib/cpus/aarch64/cortex_a720.S
View file

@ -26,6 +26,12 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720
#endif /* WORKAROUND_CVE_2022_23960 */
workaround_reset_start cortex_a720, ERRATUM(2844092), ERRATA_A720_2844092
sysreg_bit_set CORTEX_A720_CPUACTLR4_EL1, BIT(11)
workaround_reset_end cortex_a720, ERRATUM(2844092)
check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1)
workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083
/* Erratum 2926083 workaround is required only if SPE is enabled */
#if ENABLE_SPE_FOR_NS != 0

4
lib/cpus/cpu-ops.mk
View file

@ -956,6 +956,10 @@ CPU_FLAG_LIST += ERRATA_A715_2561034
# only to revision r0p0, r1p0 and r1p1. It is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_A715_2728106
# Flag to apply erratum 2844092 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_A720_2844092
# Flag to apply erratum 2926083 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_A720_2926083