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12140908a5
Cortex-A720 erratum 2844092 is a Cat B erratum that is present in revisions r0p0, r0p1 and is fixed in r0p2. The workaround is to set bit[11] of CPUACTLR4_EL1 register. SDEN documentation: https://developer.arm.com/documentation/SDEN-2439421/latest Change-Id: I3d8eacb26cba42774f1f31c3aae2a0e6fecec614 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
41 lines
1.7 KiB
C
41 lines
1.7 KiB
C
/*
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* Copyright (c) 2021-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A720_H
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#define CORTEX_A720_H
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#define CORTEX_A720_MIDR U(0x410FD810)
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/* Cortex A720 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_A720_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Auxiliary Control register 1 specific definitions.
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******************************************************************************/
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#define CORTEX_A720_CPUACTLR_EL1 S3_0_C15_C1_0
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_A720_CPUACTLR2_EL1 S3_0_C15_C1_1
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/*******************************************************************************
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* CPU Auxiliary Control register 4 specific definitions.
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******************************************************************************/
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#define CORTEX_A720_CPUACTLR4_EL1 S3_0_C15_C1_3
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_A720_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A720_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#endif /* CORTEX_A720_H */
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