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u-boot/arch
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Paul Barker 9d81a9ff99 arm: renesas: Fix RZ/G2L GICR base address 
When support for the Renesas RZ/G2L SoC was added, the GICR base address
for CPU1 was accidentally used. We should instead supply the GICR base
address for CPU0 so that interrupts are correctly configured for the
CPU core that U-Boot is actually using.

Fixes: 387d4275ab ("arm: rmobile: Add basic RZ/G2L family support")
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-11-10 19:36:54 +01:00
..
arc dts: Deduplicate dtbs target 2024-10-14 19:32:04 -06:00
arm arm: renesas: Fix RZ/G2L GICR base address 2024-11-10 19:36:54 +01:00
m68k m68k: asm/ptrace.h: include linux/types.h 2024-10-23 06:52:38 +02:00
microblaze dts: Deduplicate dtbs target 2024-10-14 19:32:04 -06:00
mips CONFIG_SYS_NONCACHED_MEMORY: Move prototypes to include/cpu_func.h for consistency 2024-10-29 16:17:18 -06:00
nios2 dts: Deduplicate dtbs target 2024-10-14 19:32:04 -06:00
powerpc dts: Deduplicate dtbs target 2024-10-14 19:32:04 -06:00
riscv riscv: Introduce configuration for 64bit version Microblaze V 2024-11-06 19:42:54 +08:00
sandbox test: efi: boot: Set up an image suitable for EFI testing 2024-11-09 10:01:47 +01:00
sh dts: Deduplicate dtbs target 2024-10-14 19:32:04 -06:00
x86 x86: coreboot: Enable support for the configuration editor 2024-11-03 21:27:12 -06:00
xtensa dts: Deduplicate dtbs target 2024-10-14 19:32:04 -06:00
.gitignore
Kconfig sandbox: virtio: Disable the sandbox virtio blk device 2024-11-09 10:01:47 +01:00
Kconfig.nxp
u-boot-elf.lds