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61d5c543f3
Andes CPU supports cache and TLB ECC. Enable them by default. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
64 lines
1.6 KiB
C
64 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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/* CPU specific code */
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#include <cpu_func.h>
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#include <irq_func.h>
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#include <asm/cache.h>
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#include <asm/csr.h>
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#include <asm/arch-andes/csr.h>
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/*
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* cleanup_before_linux() is called just before we call linux
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* it prepares the processor for linux
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*
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* we disable interrupt and caches.
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*/
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int cleanup_before_linux(void)
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{
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disable_interrupts();
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cache_flush();
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return 0;
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}
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void harts_early_init(void)
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{
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/* Enable I/D-cache in SPL */
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if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
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unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
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unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL);
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mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \
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MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \
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MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \
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MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN);
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if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
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mcache_ctl_val |= MCACHE_CTL_IC_EN;
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if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
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mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN);
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csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
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if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
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/*
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* Check mcache_ctl.DC_COHEN, we assume this platform does
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* not support CM if the bit is hard-wired to 0.
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*/
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if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
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/* Wait for DC_COHSTA bit to be set */
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while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA));
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}
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}
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mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
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csr_write(CSR_MMISC_CTL, mmisc_ctl_val);
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}
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}
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