Leo Yu-Chi Liang 61d5c543f3 andes: cpu: Enable cache and TLB ECC support ... Andes CPU supports cache and TLB ECC. Enable them by default. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>		2023-12-27 17:29:07 +08:00
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cache.c	riscv: Remove common.h usage	2023-10-24 16:34:45 -04:00
cpu.c	andes: cpu: Enable cache and TLB ECC support	2023-12-27 17:29:07 +08:00
Kconfig	riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode	2023-10-04 18:23:54 +08:00
Makefile	riscv: Rename Andes cpu and board names	2023-02-17 19:07:48 +08:00
spl.c	riscv: Remove common.h usage	2023-10-24 16:34:45 -04:00