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5769328fab
Add R-Car Gen4 APMU controller remoteproc driver capable of starting the Cortex-R52 cores in Renesas R8A779G0 V4H/V4M SoC. The APMU IP is in fact a power management unit capable of additional operations, but those are not used by U-Boot so far. This requires slight adjustment to the SPL entry point code, as that is being executed on the Cortex-R52 #0 and the Cortex-R52 #0 enters an endless loop once it starts the rest of the SPL on Cortex-A76 core. The endless loop now checks for content of APMU CRBARP registers and tests whether valid VLD_BARP and BAREN_VALID bits are set, if so, the Cortex-R52 core exits the endless loop and jumps to address started in CRBARP[31:18] register in ARM mode, which is a trampoline code to jump to the final entry point. The trampoline code is in place to avoid limitation of CRBARP[31:18] address field, which limits the core start address to memory addresses aligned to 0x40000 or 256 kiB . The trampoline is placed at 0x40000 aligned address and jumps to the final entry point, which can be at an address with arbitrary alignment at instruction granularity. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
266 lines
7.1 KiB
C
266 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#include <asm/io.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <errno.h>
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#include <hang.h>
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#include <linux/iopoll.h>
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#include <linux/sizes.h>
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#include <malloc.h>
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#include <remoteproc.h>
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/* R-Car V4H/V4M contain 3 clusters / 3 cores */
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#define RCAR4_CR52_CORES 3
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/* Reset Control Register for Cortex-R52 #n */
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#define APMU_CRRSTCTRL(n) (0x304 + ((n) * 0x40))
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#define APMU_CRRSTCTRL_CR52RST BIT(0)
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/* Base Address Register for Cortex-R52 #n */
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#define APMU_CRBARP(n) (0x33c + ((n) * 0x40))
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#define APMU_CRBARP_CR_VLD_BARP BIT(0)
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#define APMU_CRBARP_CR_BAREN_VALID BIT(4)
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#define APMU_CRBARP_CR_RBAR_MASK 0xfffc0000
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#define APMU_CRBARP_CR_RBAR_ALIGN 0x40000
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/**
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* struct renesas_apmu_rproc_privdata - remote processor private data
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* @regs: controller registers
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* @core_id: CPU core id
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* @trampoline: jump trampoline code
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*/
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struct renesas_apmu_rproc_privdata {
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void __iomem *regs;
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ulong core_id;
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u32 *trampoline;
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};
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/*
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* CRBARP address is aligned to 0x40000 / 256 kiB , this trampoline
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* allows arbitrary address alignment at instruction granularity.
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*/
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static const u32 renesas_apmu_rproc_trampoline[4] = {
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0xe59f0004, /* ldr r0, [pc, #4] */
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0xe1a0f000, /* mov pc, r0 */
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0xeafffffe, /* 1: b 1b */
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0xabcd1234 /* jump target (rewritten on load) */
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};
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/**
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* renesas_apmu_rproc_load() - Load the remote processor
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* @dev: corresponding remote processor device
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* @addr: Address in memory where image is stored
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* @size: Size in bytes of the image
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*
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* Return: 0 if all went ok, else corresponding -ve error
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*/
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static int renesas_apmu_rproc_load(struct udevice *dev, ulong addr, ulong size)
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{
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struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev);
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u32 trampolineaddr = (u32)(uintptr_t)(priv->trampoline);
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priv->trampoline[3] = addr;
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flush_dcache_range(trampolineaddr,
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trampolineaddr +
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sizeof(renesas_apmu_rproc_trampoline));
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/* CR52 boot address set */
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writel(trampolineaddr | APMU_CRBARP_CR_VLD_BARP,
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priv->regs + APMU_CRBARP(priv->core_id));
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writel(trampolineaddr | APMU_CRBARP_CR_VLD_BARP | APMU_CRBARP_CR_BAREN_VALID,
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priv->regs + APMU_CRBARP(priv->core_id));
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return 0;
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}
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/**
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* renesas_apmu_rproc_start() - Start the remote processor
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* @dev: corresponding remote processor device
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*
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* Return: 0 if all went ok, else corresponding -ve error
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*/
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static int renesas_apmu_rproc_start(struct udevice *dev)
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{
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struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev);
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/* Clear APMU_CRRSTCTRL_CR52RST, the only bit in this register */
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writel(0, priv->regs + APMU_CRRSTCTRL(priv->core_id));
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return 0;
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}
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/**
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* renesas_apmu_rproc_stop() - Stop the remote processor
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* @dev: corresponding remote processor device
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*
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* Return: 0 if all went ok, else corresponding -ve error
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*/
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static int renesas_apmu_rproc_stop(struct udevice *dev)
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{
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struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev);
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/* Set APMU_CRRSTCTRL_CR52RST, the only bit in this register */
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writel(APMU_CRRSTCTRL_CR52RST,
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priv->regs + APMU_CRRSTCTRL(priv->core_id));
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return 0;
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}
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/**
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* renesas_apmu_rproc_reset() - Reset the remote processor
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* @dev: corresponding remote processor device
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*
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* Return: 0 if all went ok, else corresponding -ve error
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*/
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static int renesas_apmu_rproc_reset(struct udevice *dev)
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{
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renesas_apmu_rproc_stop(dev);
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renesas_apmu_rproc_start(dev);
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return 0;
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}
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/**
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* renesas_apmu_rproc_is_running() - Is the remote processor running
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* @dev: corresponding remote processor device
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*
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* Return: 0 if the remote processor is running, 1 otherwise
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*/
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static int renesas_apmu_rproc_is_running(struct udevice *dev)
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{
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struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev);
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return readl(priv->regs + APMU_CRRSTCTRL(priv->core_id)) &
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APMU_CRRSTCTRL_CR52RST;
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}
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/**
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* renesas_apmu_rproc_init() - Initialize the remote processor CRBAR registers
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* @dev: corresponding remote processor device
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*
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* Return: 0 if all went ok, else corresponding -ve error
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*/
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static int renesas_apmu_rproc_init(struct udevice *dev)
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{
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struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev);
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/* If the core is running already, do nothing. */
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if (renesas_apmu_rproc_is_running(dev))
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return 0;
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/* Clear and invalidate CRBARP content */
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writel(0, priv->regs + APMU_CRBARP(priv->core_id));
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return 0;
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}
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/**
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* renesas_apmu_rproc_device_to_virt() - Convert device address to virtual address
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* @dev: corresponding remote processor device
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* @da: device address
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* @size: Size of the memory region @da is pointing to
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*
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* Return: converted virtual address
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*/
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static void *renesas_apmu_rproc_device_to_virt(struct udevice *dev, ulong da,
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ulong size)
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{
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/*
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* The Cortex R52 and A76 share the same address space,
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* this operation is a no-op.
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*/
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return (void *)da;
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}
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static const struct dm_rproc_ops renesas_apmu_rproc_ops = {
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.init = renesas_apmu_rproc_init,
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.load = renesas_apmu_rproc_load,
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.start = renesas_apmu_rproc_start,
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.stop = renesas_apmu_rproc_stop,
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.reset = renesas_apmu_rproc_reset,
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.is_running = renesas_apmu_rproc_is_running,
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.device_to_virt = renesas_apmu_rproc_device_to_virt,
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};
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/**
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* renesas_apmu_rproc_of_to_plat() - Convert OF data to platform data
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* @dev: corresponding remote processor device
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*
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* Return: 0 if all went ok, else corresponding -ve error
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*/
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static int renesas_apmu_rproc_of_to_plat(struct udevice *dev)
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{
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struct renesas_apmu_rproc_privdata *priv = dev_get_priv(dev);
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priv->core_id = dev_get_driver_data(dev);
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priv->regs = dev_read_addr_ptr(dev);
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if (!priv->regs)
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return -EINVAL;
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priv->trampoline = memalign(APMU_CRBARP_CR_RBAR_ALIGN,
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sizeof(renesas_apmu_rproc_trampoline));
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if (!priv->trampoline)
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return -ENOMEM;
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memcpy(priv->trampoline, renesas_apmu_rproc_trampoline,
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sizeof(renesas_apmu_rproc_trampoline));
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return 0;
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}
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U_BOOT_DRIVER(renesas_apmu_cr52) = {
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.name = "rcar-apmu-cr52",
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.id = UCLASS_REMOTEPROC,
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.ops = &renesas_apmu_rproc_ops,
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.of_to_plat = renesas_apmu_rproc_of_to_plat,
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.priv_auto = sizeof(struct renesas_apmu_rproc_privdata),
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};
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/**
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* renesas_apmu_rproc_bind() - Bind rproc driver to each core control
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* @dev: corresponding remote processor parent device
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*
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* Return: 0 if all went ok, else corresponding -ve error
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*/
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static int renesas_apmu_rproc_bind(struct udevice *parent)
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{
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const ulong cr52cores = RCAR4_CR52_CORES;
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ofnode pnode = dev_ofnode(parent);
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struct udevice *cdev;
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struct driver *cdrv;
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char name[32];
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ulong i;
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int ret;
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cdrv = lists_driver_lookup_name("rcar-apmu-cr52");
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if (!cdrv)
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return -ENOENT;
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for (i = 0; i < cr52cores; i++) {
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snprintf(name, sizeof(name), "rcar-apmu-cr52.%ld", i);
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ret = device_bind_with_driver_data(parent, cdrv, strdup(name),
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i, pnode, &cdev);
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if (ret)
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return ret;
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}
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return 0;
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}
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static const struct udevice_id renesas_apmu_rproc_ids[] = {
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{ .compatible = "renesas,r8a779g0-cr52" },
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{ .compatible = "renesas,r8a779h0-cr52" },
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{ }
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};
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U_BOOT_DRIVER(renesas_apmu_rproc) = {
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.name = "rcar-apmu-rproc",
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.of_match = renesas_apmu_rproc_ids,
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.id = UCLASS_NOP,
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.bind = renesas_apmu_rproc_bind,
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};
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