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5769328fab
Add R-Car Gen4 APMU controller remoteproc driver capable of starting the Cortex-R52 cores in Renesas R8A779G0 V4H/V4M SoC. The APMU IP is in fact a power management unit capable of additional operations, but those are not used by U-Boot so far. This requires slight adjustment to the SPL entry point code, as that is being executed on the Cortex-R52 #0 and the Cortex-R52 #0 enters an endless loop once it starts the rest of the SPL on Cortex-A76 core. The endless loop now checks for content of APMU CRBARP registers and tests whether valid VLD_BARP and BAREN_VALID bits are set, if so, the Cortex-R52 core exits the endless loop and jumps to address started in CRBARP[31:18] register in ARM mode, which is a trampoline code to jump to the final entry point. The trampoline code is in place to avoid limitation of CRBARP[31:18] address field, which limits the core start address to memory addresses aligned to 0x40000 or 256 kiB . The trampoline is placed at 0x40000 aligned address and jumps to the final entry point, which can be at an address with arbitrary alignment at instruction granularity. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> |
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| .. | ||
| ipu_rproc.c | ||
| k3_system_controller.c | ||
| Kconfig | ||
| Makefile | ||
| pru_rproc.c | ||
| renesas_apmu.c | ||
| rproc-elf-loader.c | ||
| rproc-uclass.c | ||
| sandbox_testproc.c | ||
| stm32_copro.c | ||
| ti_k3_arm64_rproc.c | ||
| ti_k3_dsp_rproc.c | ||
| ti_k3_r5f_rproc.c | ||
| ti_power_proc.c | ||
| ti_sci_proc.h | ||