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5392ad2fd9
Explicitly flush icache on the CR52 core before jumping to the next stage software to make sure it does not contain any invalid content. Explicitly flash and invalidate dcache on the CA76 core both over the trampoline buffer and over the CR52 firmware, and then trigger full system synchronization, to make sure the data surely land in DRAM, from where the CR52 can surely pick them up. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> |
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| .. | ||
| ipu_rproc.c | ||
| k3_system_controller.c | ||
| Kconfig | ||
| Makefile | ||
| pru_rproc.c | ||
| renesas_apmu.c | ||
| rproc-elf-loader.c | ||
| rproc-uclass.c | ||
| sandbox_testproc.c | ||
| stm32_copro.c | ||
| ti_k3_arm64_rproc.c | ||
| ti_k3_dsp_rproc.c | ||
| ti_k3_r5f_rproc.c | ||
| ti_power_proc.c | ||
| ti_sci_proc.h | ||