Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-04-11 07:24:46 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

remoteproc: renesas: Synchronize caches across cores

Browse source 
Explicitly flush icache on the CR52 core before jumping to the next
stage software to make sure it does not contain any invalid content.
Explicitly flash and invalidate dcache on the CA76 core both over the
trampoline buffer and over the CR52 firmware, and then trigger full
system synchronization, to make sure the data surely land in DRAM,
from where the CR52 can surely pick them up.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2025-01-29 22:54:50 +01:00
parent 97c125e6bb
commit 5392ad2fd9
2 changed files with 18 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
arch/arm/mach-renesas/include/mach/boot0.h
View file

@ -34,7 +34,7 @@ _start:
.inst 0xe380070a /* orr r0, r0, #0x280000 */
/* APMU_RVBARPLC0 = (address of 'b reset' below) | CA_CORE0_VLD_RVBARP */
.inst 0xe28f3088 /* add r3, pc, #0x88 */
.inst 0xe28f30a8 /* add r3, pc, #0xa8 */
.inst 0xe3833001 /* orr r3, r3, #1 */
.inst 0xe5843038 /* str r3, [r4, #56] @ 0x38 */
@ -75,12 +75,22 @@ _start:
.inst 0xe20230ff /* and r3, r2, #255 @ 0xff */
.inst 0xe3530011 /* cmp r3, #17 */
.inst 0x1afffffb /* bne 78 <reset-0x28> */
/* Invalidate icache before jump to follow up software */
.inst 0xe3a00000 /* mov r0, #0 */
.inst 0xee070f15 /* mcr 15, 0, r0, cr7, cr5, {0} */
.inst 0xf57ff04f /* dsb sy */
.inst 0xf57ff06f /* isb sy */
/* Jump to follow up software */
.inst 0xe1a02922 /* lsr r2, r2, #18 */
.inst 0xe1a02902 /* lsl r2, r2, #18 */
.inst 0xe1a0f002 /* mov pc, r2 */
.inst 0xeafffffe /* b 94 <reset-0xc> */
.inst 0xe1a00000 /* nop @ (mov r0, r0) */
.inst 0xe1a00000 /* nop @ (mov r0, r0) */
.inst 0xe1a00000 /* nop @ (mov r0, r0) */
.inst 0xe1a00000 /* nop @ (mov r0, r0) */
.inst 0xe1a00000 /* nop @ (mov r0, r0) */
.inst 0xe1a00000 /* nop @ (mov r0, r0) */
/* Offset 0xa0 */
#endif
b reset

7
drivers/remoteproc/renesas_apmu.c
View file

@ -68,6 +68,13 @@ static int renesas_apmu_rproc_load(struct udevice *dev, ulong addr, ulong size)
flush_dcache_range(trampolineaddr,
trampolineaddr +
sizeof(renesas_apmu_rproc_trampoline));
invalidate_dcache_range(trampolineaddr,
trampolineaddr +
sizeof(renesas_apmu_rproc_trampoline));
flush_dcache_range(addr, addr + size);
invalidate_dcache_range(addr, addr + size);
asm volatile("dsb sy\n");
asm volatile("isb sy\n");
/* CR52 boot address set */
writel(trampolineaddr | APMU_CRBARP_CR_VLD_BARP,