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d13e67c24d
Add support for PHYTEC phyCORE-AM62A7 SoM. Supported features: - 2GB LPDDR4 RAM - eMMC - External SD - Ethernet - debug UART Signed-off-by: Garrett Giordano <ggiordano@phytec.com> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
64 lines
1.4 KiB
C
64 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright (C) 2024 PHYTEC America LLC
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* Author: Garrett Giordano <ggiordano@phytec.com>
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*/
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#include <spl.h>
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#include <fdt_support.h>
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#include "../common/am6_som_detection.h"
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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return fdtdec_setup_mem_size_base();
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}
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int dram_init_banksize(void)
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{
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return fdtdec_setup_memory_banksize();
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}
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#define CTRLMMR_USB0_PHY_CTRL 0x43004008
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#define CTRLMMR_USB1_PHY_CTRL 0x43004018
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#define CORE_VOLTAGE 0x80000000
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#ifdef CONFIG_SPL_BOARD_INIT
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void spl_board_init(void)
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{
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u32 val;
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/* Set USB0 PHY core voltage to 0.85V */
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val = readl(CTRLMMR_USB0_PHY_CTRL);
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val &= ~(CORE_VOLTAGE);
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writel(val, CTRLMMR_USB0_PHY_CTRL);
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/* Set USB1 PHY core voltage to 0.85V */
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val = readl(CTRLMMR_USB1_PHY_CTRL);
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val &= ~(CORE_VOLTAGE);
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writel(val, CTRLMMR_USB1_PHY_CTRL);
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if (IS_ENABLED(CONFIG_SPL_ETH))
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/* Init DRAM size for R5/A53 SPL */
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dram_init_banksize();
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/* We have 32k crystal, so lets enable it */
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val = readl(MCU_CTRL_LFXOSC_CTRL);
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val &= ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL);
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writel(val, MCU_CTRL_LFXOSC_CTRL);
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/* Add any TRIM needed for the crystal here.. */
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/* Make sure to mux up to take the SoC 32k from the crystal */
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writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
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MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
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/* Init DRAM size for R5/A53 SPL */
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dram_init_banksize();
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}
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#endif
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