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board: phytec: am62a7: Add PHYTEC phyCORE-AM62A7 SoM

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Add support for PHYTEC phyCORE-AM62A7 SoM.

Supported features:
  - 2GB LPDDR4 RAM
  - eMMC
  - External SD
  - Ethernet
  - debug UART

Signed-off-by: Garrett Giordano <ggiordano@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
This commit is contained in:
Garrett Giordano 2024-11-18 15:16:05 -08:00 • committed by Tom Rini
parent deb9a07cf1
commit d13e67c24d
19 changed files with 6502 additions and 1 deletions
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4
arch/arm/dts/Makefile
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@ -1183,7 +1183,9 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-r5-sk.dtb \
k3-am625-verdin-r5.dtb \
k3-am625-r5-phycore-som-2gb.dtb
dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-r5-sk.dtb
dtb-$(CONFIG_SOC_K3_AM62A7) += \
k3-am62a7-r5-sk.dtb \
k3-am62a7-r5-phycore-som-2gb.dtb
dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb

454
arch/arm/dts/k3-am62a-phycore-som-binman.dtsi Normal file
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@ -0,0 +1,454 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Based on k3-am62a-sk-binman.dtsi
*
* Copyright (C) 2024 PHYTEC America LLC
* Author: Garrett Giordano <ggiordano@phytec.com>
*/
#include "k3-binman.dtsi"
#ifdef CONFIG_TARGET_PHYCORE_AM62AX_R5
&rcfg_yaml_tifs {
config = "tifs-rm-cfg.yaml";
};
&binman {
tiboot3-am62ax-hs-phycore-som.bin {
filename = "tiboot3-am62ax-hs-phycore-som.bin";
ti-secure-rom {
content = <&u_boot_spl>, <&ti_fs_enc>, <&combined_tifs_cfg>,
<&combined_dm_cfg>, <&sysfw_inner_cert>;
combined;
dm-data;
sysfw-inner-cert;
keyfile = "custMpk.pem";
sw-rev = <1>;
content-sbl = <&u_boot_spl>;
content-sysfw = <&ti_fs_enc>;
content-sysfw-data = <&combined_tifs_cfg>;
content-sysfw-inner-cert = <&sysfw_inner_cert>;
content-dm-data = <&combined_dm_cfg>;
load = <0x43c00000>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c3a800>;
};
u_boot_spl: u-boot-spl {
no-expanded;
};
ti_fs_enc: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
sysfw_inner_cert: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
&binman {
tiboot3-am62ax-hs-fs-phycore-som.bin {
filename = "tiboot3-am62ax-hs-fs-phycore-som.bin";
symlink = "tiboot3.bin";
ti-secure-rom {
content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>,
<&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>;
combined;
dm-data;
sysfw-inner-cert;
keyfile = "custMpk.pem";
sw-rev = <1>;
content-sbl = <&u_boot_spl_fs>;
content-sysfw = <&ti_fs_enc_fs>;
content-sysfw-data = <&combined_tifs_cfg_fs>;
content-sysfw-inner-cert = <&sysfw_inner_cert_fs>;
content-dm-data = <&combined_dm_cfg_fs>;
load = <0x43c00000>;
load-sysfw = <0x40000>;
load-sysfw-data = <0x67000>;
load-dm-data = <0x43c3a800>;
};
u_boot_spl_fs: u-boot-spl {
no-expanded;
};
ti_fs_enc_fs: ti-fs-enc.bin {
filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-enc.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_fs: combined-tifs-cfg.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
sysfw_inner_cert_fs: sysfw-inner-cert {
filename = "ti-sysfw/ti-fs-firmware-am62ax-hs-fs-cert.bin";
type = "blob-ext";
optional;
};
combined_dm_cfg_fs: combined-dm-cfg.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
&binman {
tiboot3-am62ax-gp-phycore-som.bin {
filename = "tiboot3-am62ax-gp-phycore-som.bin";
ti-secure-rom {
content = <&u_boot_spl_unsigned>, <&ti_fs_gp>,
<&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>;
combined;
dm-data;
content-sbl = <&u_boot_spl_unsigned>;
load = <0x43c00000>;
content-sysfw = <&ti_fs_gp>;
load-sysfw = <0x40000>;
content-sysfw-data = <&combined_tifs_cfg_gp>;
load-sysfw-data = <0x67000>;
content-dm-data = <&combined_dm_cfg_gp>;
load-dm-data = <0x43c3a800>;
sw-rev = <1>;
keyfile = "ti-degenerate-key.pem";
};
u_boot_spl_unsigned: u-boot-spl {
no-expanded;
};
ti_fs_gp: ti-fs-gp.bin {
filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin";
type = "blob-ext";
optional;
};
combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin {
filename = "combined-tifs-cfg.bin";
type = "blob-ext";
};
combined_dm_cfg_gp: combined-dm-cfg-gp.bin {
filename = "combined-dm-cfg.bin";
type = "blob-ext";
};
};
};
#endif
#ifdef CONFIG_TARGET_PHYCORE_AM62AX_A53
#define SPL_AM62A7_PHYBOARD_LYRA_DTB "spl/dts/ti/k3-am62a7-phyboard-lyra-rdk.dtb"
#define AM62A7_PHYBOARD_LYRA_DTB "u-boot.dtb"
&binman {
ti-dm {
filename = "ti-dm.bin";
blob-ext {
filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f";
optional;
};
};
tifsstub-hs {
filename = "tifsstub.bin_hs";
ti-secure-rom {
content = <&tifsstub_hs_cert>;
core = "secure";
load = <0x60000>;
sw-rev = <CONFIG_K3_X509_SWRV>;
keyfile = "custMpk.pem";
countersign;
tifsstub;
};
tifsstub_hs_cert: tifsstub-hs-cert.bin {
filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin";
type = "blob-ext";
optional;
};
tifsstub_hs_enc: tifsstub-hs-enc.bin {
filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin";
type = "blob-ext";
optional;
};
};
tifsstub-fs {
filename = "tifsstub.bin_fs";
tifsstub_fs_cert: tifsstub-fs-cert.bin {
filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-cert.bin";
type = "blob-ext";
optional;
};
tifsstub_fs_enc: tifsstub-fs-enc.bin {
filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-hs-enc.bin";
type = "blob-ext";
optional;
};
};
tifsstub-gp {
filename = "tifsstub.bin_gp";
ti-secure-rom {
content = <&tifsstub_gp>;
core = "secure";
load = <0x60000>;
sw-rev = <CONFIG_K3_X509_SWRV>;
keyfile = "ti-degenerate-key.pem";
tifsstub;
};
tifsstub_gp: tifsstub-gp.bin {
filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin";
type = "blob-ext";
optional;
};
};
ti-spl {
insert-template = <&ti_spl_template>;
fit {
images {
tifsstub-hs {
description = "TIFSSTUB";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-hs";
load = <0x9ca00000>;
entry = <0x9ca00000>;
blob-ext {
filename = "tifsstub.bin_hs";
};
};
tifsstub-fs {
description = "TIFSSTUB";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-fs";
load = <0x9ca00000>;
entry = <0x9ca00000>;
blob-ext {
filename = "tifsstub.bin_fs";
};
};
tifsstub-gp {
description = "TIFSSTUB";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-gp";
load = <0x9ca00000>;
entry = <0x9ca00000>;
blob-ext {
filename = "tifsstub.bin_gp";
};
};
dm {
ti-secure {
content = <&dm>;
keyfile = "custMpk.pem";
};
dm: ti-dm {
filename = "ti-dm.bin";
};
};
fdt-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&spl_am62a7_phyboard_lyra_dtb>;
keyfile = "custMpk.pem";
};
spl_am62a7_phyboard_lyra_dtb: blob-ext {
filename = SPL_AM62A7_PHYBOARD_LYRA_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
firmware = "atf";
loadables = "tee", "dm", "spl",
"tifsstub-hs", "tifsstub-fs", "tifsstub-gp";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot {
insert-template = <&u_boot_template>;
fit {
images {
uboot {
description = "U-Boot for AM62Ax board";
};
fdt-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
ti-secure {
content = <&am62a7_phyboard_lyra_dtb>;
keyfile = "custMpk.pem";
};
am62a7_phyboard_lyra_dtb: blob-ext {
filename = AM62A7_PHYBOARD_LYRA_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
&binman {
ti-spl_unsigned {
insert-template = <&ti_spl_unsigned_template>;
fit {
images {
tifsstub-hs {
description = "tifsstub";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-hs";
load = <0x9ca00000>;
entry = <0x9ca00000>;
blob-ext {
filename = "tifsstub.bin_hs";
};
};
tifsstub-fs {
description = "tifsstub";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-fs";
load = <0x9ca00000>;
entry = <0x9ca00000>;
blob-ext {
filename = "tifsstub.bin_fs";
};
};
tifsstub-gp {
description = "tifsstub";
type = "firmware";
arch = "arm32";
compression = "none";
os = "tifsstub-gp";
load = <0x9ca00000>;
entry = <0x9ca00000>;
blob-ext {
filename = "tifsstub.bin_gp";
};
};
dm {
ti-dm {
filename = "ti-dm.bin";
};
};
fdt-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
spl_am62a7_phyboard_lyra_dtb_unsigned: blob {
filename = SPL_AM62A7_PHYBOARD_LYRA_DTB;
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
firmware = "atf";
loadables = "tee", "dm", "spl",
"tifsstub-hs", "tifsstub-fs", "tifsstub-gp";
fdt = "fdt-0";
};
};
};
};
};
&binman {
u-boot_unsigned {
insert-template = <&u_boot_unsigned_template>;
fit {
images {
uboot {
description = "U-Boot for AM62Ax board";
};
fdt-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
filename = AM62A7_PHYBOARD_LYRA_DTB;
};
hash {
algo = "crc32";
};
};
};
configurations {
default = "conf-0";
conf-0 {
description = "k3-am62a7-phyboard-lyra-rdk";
firmware = "uboot";
loadables = "uboot";
fdt = "fdt-0";
};
};
};
};
};
#endif

2798
arch/arm/dts/k3-am62a-phycore-som-ddr4-2gb.dtsi Normal file
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252
arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi Normal file
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@ -0,0 +1,252 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* phyCORE-AM62Ax dts file for SPLs
* Copyright (C) 2024 PHYTEC America LLC
* Author: Garrett Giordano <ggiordano@phytec.com>
*
* Product homepage:
* https://www.phytec.com/product/phycore-am62ax
*/
#include "k3-am62a-phycore-som-binman.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &main_timer0;
};
aliases {
mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
memory@80000000 {
bootph-all;
};
};
&cbass_main {
bootph-all;
};
&cbass_mcu {
bootph-all;
};
&cbass_wakeup {
bootph-all;
};
&chipid {
bootph-all;
};
&cpsw3g {
bootph-all;
ethernet-ports {
bootph-all;
};
};
&cpsw3g_mdio {
bootph-all;
};
&cpsw3g_phy1 {
bootph-all;
};
&cpsw3g_phy3 {
bootph-all;
};
&cpsw_port1 {
bootph-all;
};
&cpsw_port2 {
bootph-all;
};
&dmsc {
bootph-all;
};
&dmss {
bootph-all;
};
&fss {
bootph-all;
};
&k3_pds {
bootph-all;
};
&k3_clks {
bootph-all;
};
&k3_reset {
bootph-all;
};
&main_bcdma {
bootph-all;
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
"ringrt", "cfg", "tchan", "rchan";
};
&main_conf {
bootph-all;
};
&main_gpio0 {
bootph-all;
};
&main_i2c0 {
bootph-all;
};
&main_i2c0_pins_default {
bootph-all;
};
&main_mdio1_pins_default {
bootph-all;
};
&main_mmc0_pins_default {
bootph-all;
};
&main_mmc1_pins_default {
bootph-all;
};
&main_pktdma {
bootph-all;
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>,
<0x00 0x485e0000 0x00 0x20000>,
<0x00 0x484a0000 0x00 0x4000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x4000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
"cfg", "tchan", "rchan", "rflow";
};
&main_pmx0 {
bootph-all;
};
&main_rgmii1_pins_default {
bootph-all;
};
&main_timer0 {
bootph-all;
};
&main_uart0 {
bootph-all;
};
&main_uart0_pins_default {
bootph-all;
};
&main_uart1 {
bootph-all;
};
&mcu_pmx0 {
bootph-all;
};
&ospi0_pins_default {
bootph-all;
};
&ospi0 {
bootph-all;
flash@0 {
bootph-all;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ospi.tiboot3";
reg = <0x00000 0x80000>;
};
partition@80000 {
label = "ospi.tispl";
reg = <0x080000 0x200000>;
};
partition@280000 {
label = "ospi.u-boot";
reg = <0x280000 0x400000>;
};
partition@680000 {
label = "ospi.env";
reg = <0x680000 0x40000>;
};
partition@6c0000 {
label = "ospi.env.backup";
reg = <0x6c0000 0x40000>;
};
};
};
};
&phy_gmii_sel {
bootph-all;
};
&sdhci0 {
bootph-all;
};
&sdhci1 {
bootph-all;
};
&secure_proxy_main {
bootph-all;
};
&usbss0 {
bootph-all;
};
&usb0 {
dr_mode = "peripheral";
bootph-all;
};
&vcc_3v3_mmc {
bootph-all;
};
&wkup_conf {
bootph-all;
};
&wkup_uart0 {
bootph-all;
};

137
arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts Normal file
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@ -0,0 +1,137 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* phyCORE-AM62Ax dts file for R5 SPL
* Copyright (C) 2024 PHYTEC America LLC
* Author: Garrett Giordano <ggiordano@phytec.com>
*
* Product homepage:
* https://www.phytec.com/product/phycore-am62ax
*/
#include "k3-am62a7-phyboard-lyra-rdk.dts"
#include "k3-am62a-phycore-som-ddr4-2gb.dtsi"
#include "k3-am62a-ddr.dtsi"
#include "k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
serial0 = &wkup_uart0;
serial3 = &main_uart1;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1200000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
bootph-pre-ram;
};
};
&cbass_main {
bootph-pre-ram;
sa3_secproxy: secproxy@44880000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg = <0x00 0x44880000 0x00 0x20000>,
<0x0 0x44860000 0x0 0x20000>,
<0x0 0x43600000 0x0 0x10000>;
reg-names = "rt", "scfg", "target_data";
bootph-pre-ram;
};
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>,
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&main_bcdma {
ti,sci = <&dm_tifs>;
};
&main_pktdma {
ti,sci = <&dm_tifs>;
};
&main_pmx0 {
bootph-pre-ram;
};
/* Main UART1 is used for TIFS firmware logs */
&main_uart1 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
status = "okay";
bootph-pre-ram;
};
&mcu_pmx0 {
status = "okay";
bootph-pre-ram;
wkup_uart0_pins_default: wkup-uart0-pins-default {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */
AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
>;
bootph-pre-ram;
};
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x08000000>;
};
/* WKUP UART0 is used for DM firmware logs */
&wkup_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
bootph-pre-ram;
};

21
arch/arm/mach-k3/am62ax/Kconfig
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@ -30,8 +30,29 @@ config TARGET_AM62A7_R5_EVM
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
config TARGET_PHYCORE_AM62AX_A53
bool "PHYTEC phyCORE-AM62Ax running on A53"
select ARM64
select BINMAN
select OF_SYSTEM_SETUP
imply OF_UPSTREAM
imply BOARD
imply SPL_BOARD
config TARGET_PHYCORE_AM62AX_R5
bool "PHYTEC phyCORE-AM62Ax running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_DDRSS
select BINMAN
imply SYS_K3_SPL_ATF
endchoice
source "board/ti/am62ax/Kconfig"
source "board/phytec/phycore_am62ax/Kconfig"
endif

37
board/phytec/phycore_am62ax/Kconfig Normal file
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@ -0,0 +1,37 @@
# SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#
# Copyright (C) 2024 PHYTEC America LLC
# Author: Garrett Giordano <ggiordano@phytec.com>
if TARGET_PHYCORE_AM62AX_A53
config SYS_BOARD
default "phycore_am62ax"
config SYS_VENDOR
default "phytec"
config SYS_CONFIG_NAME
default "phycore_am62ax"
source "board/phytec/common/Kconfig"
endif
if TARGET_PHYCORE_AM62AX_R5
config SYS_BOARD
default "phycore_am62ax"
config SYS_VENDOR
default "phytec"
config SYS_CONFIG_NAME
default "phycore_am62ax"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
source "board/phytec/common/Kconfig"
endif

14
board/phytec/phycore_am62ax/MAINTAINERS Normal file
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@ -0,0 +1,14 @@
phyCORE-AM62ax
M: Garrett Giordano <ggiordano@phytec.com>
M: Wadim Egorov <w.egorov@phytec.de>
W: https://www.phytec.com/product/phycore-am62a
S: Maintained
F: arch/arm/dts/k3-am62a-phycore-som-binman.dtsi
F: arch/arm/dts/k3-am62a-phycore-som-ddr4-2gb.dtsit.dtsi
F: arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
F: arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts
F: board/phytec/phycore_am62ax/
F: configs/phycore_am62ax_a53_defconfig
F: configs/phycore_am62ax_r5_defconfig
F: include/configs/phycore_am62ax.h
F: doc/board/phytec/phycore-am62ax.rst

6
board/phytec/phycore_am62ax/Makefile Normal file
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@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#
# Copyright (C) 2024 PHYTEC America LLC
# Author: Garrett Giordano <ggiordano@phytec.com>
obj-y += phycore-am62ax.o

36
board/phytec/phycore_am62ax/board-cfg.yaml Normal file
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@ -0,0 +1,36 @@
# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
#
# Board configuration for AM62ax
#
---
board-cfg:
rev:
boardcfg_abi_maj: 0x0
boardcfg_abi_min: 0x1
control:
subhdr:
magic: 0xC1D3
size: 7
main_isolation_enable: 0x5A
main_isolation_hostid: 0x2
secproxy:
subhdr:
magic: 0x1207
size: 7
scaling_factor: 0x1
scaling_profile: 0x1
disable_main_nav_secure_proxy: 0
msmc:
subhdr:
magic: 0xA5C3
size: 5
msmc_cache_size: 0x10
debug_cfg:
subhdr:
magic: 0x020C
size: 8
trace_dst_enables: 0x00
trace_src_enables: 0x00

64
board/phytec/phycore_am62ax/phycore-am62ax.c Normal file
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@ -0,0 +1,64 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2024 PHYTEC America LLC
* Author: Garrett Giordano <ggiordano@phytec.com>
*/
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <spl.h>
#include <fdt_support.h>
#include "../common/am6_som_detection.h"
int board_init(void)
{
return 0;
}
int dram_init(void)
{
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
}
#define CTRLMMR_USB0_PHY_CTRL 0x43004008
#define CTRLMMR_USB1_PHY_CTRL 0x43004018
#define CORE_VOLTAGE 0x80000000
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void)
{
u32 val;
/* Set USB0 PHY core voltage to 0.85V */
val = readl(CTRLMMR_USB0_PHY_CTRL);
val &= ~(CORE_VOLTAGE);
writel(val, CTRLMMR_USB0_PHY_CTRL);
/* Set USB1 PHY core voltage to 0.85V */
val = readl(CTRLMMR_USB1_PHY_CTRL);
val &= ~(CORE_VOLTAGE);
writel(val, CTRLMMR_USB1_PHY_CTRL);
if (IS_ENABLED(CONFIG_SPL_ETH))
/* Init DRAM size for R5/A53 SPL */
dram_init_banksize();
/* We have 32k crystal, so lets enable it */
val = readl(MCU_CTRL_LFXOSC_CTRL);
val &= ~(MCU_CTRL_LFXOSC_32K_DISABLE_VAL);
writel(val, MCU_CTRL_LFXOSC_CTRL);
/* Add any TRIM needed for the crystal here.. */
/* Make sure to mux up to take the SoC 32k from the crystal */
writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
/* Init DRAM size for R5/A53 SPL */
dram_init_banksize();
}
#endif

14
board/phytec/phycore_am62ax/phycore_am62ax.env Normal file
View file

@ -0,0 +1,14 @@
fdtaddr=0x88000000
loadaddr=0x82000000
scriptaddr=0x80000000
fdt_addr_r=0x88000000
kernel_addr_r=0x82000000
ramdisk_addr_r=0x88080000
fdtoverlay_addr_r=0x89000000
fdtfile=CONFIG_DEFAULT_FDT_FILE
mmcdev=1
mmcroot=2
mmcpart=1
console=ttyS2,115200n8
earlycon=ns16550a,mmio32,0x02800000

12
board/phytec/phycore_am62ax/pm-cfg.yaml Normal file
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@ -0,0 +1,12 @@
# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
#
# Power management configuration for AM62ax
#
---
pm-cfg:
rev:
boardcfg_abi_maj: 0x0
boardcfg_abi_min: 0x1

1047
board/phytec/phycore_am62ax/rm-cfg.yaml Normal file
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File diff suppressed because it is too large Load diff

379
board/phytec/phycore_am62ax/sec-cfg.yaml Normal file
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@ -0,0 +1,379 @@
# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
#
# Security configuration for AM62ax
#
---
sec-cfg:
rev:
boardcfg_abi_maj: 0x0
boardcfg_abi_min: 0x1
processor_acl_list:
subhdr:
magic: 0xF1EA
size: 164
proc_acl_entries:
- # 1
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 2
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 3
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 4
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 5
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 6
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 7
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 8
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 9
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 10
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 11
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 12
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 13
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 14
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 15
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 16
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 17
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 18
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 19
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 20
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 21
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 22
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 23
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 24
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 25
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 26
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 27
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 28
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 29
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 30
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 31
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
- # 32
processor_id: 0
proc_access_master: 0
proc_access_secondary: [0, 0, 0]
host_hierarchy:
subhdr:
magic: 0x8D27
size: 68
host_hierarchy_entries:
- # 1
host_id: 0
supervisor_host_id: 0
- # 2
host_id: 0
supervisor_host_id: 0
- # 3
host_id: 0
supervisor_host_id: 0
- # 4
host_id: 0
supervisor_host_id: 0
- # 5
host_id: 0
supervisor_host_id: 0
- # 6
host_id: 0
supervisor_host_id: 0
- # 7
host_id: 0
supervisor_host_id: 0
- # 8
host_id: 0
supervisor_host_id: 0
- # 9
host_id: 0
supervisor_host_id: 0
- # 10
host_id: 0
supervisor_host_id: 0
- # 11
host_id: 0
supervisor_host_id: 0
- # 12
host_id: 0
supervisor_host_id: 0
- # 13
host_id: 0
supervisor_host_id: 0
- # 14
host_id: 0
supervisor_host_id: 0
- # 15
host_id: 0
supervisor_host_id: 0
- # 16
host_id: 0
supervisor_host_id: 0
- # 17
host_id: 0
supervisor_host_id: 0
- # 18
host_id: 0
supervisor_host_id: 0
- # 19
host_id: 0
supervisor_host_id: 0
- # 20
host_id: 0
supervisor_host_id: 0
- # 21
host_id: 0
supervisor_host_id: 0
- # 22
host_id: 0
supervisor_host_id: 0
- # 23
host_id: 0
supervisor_host_id: 0
- # 24
host_id: 0
supervisor_host_id: 0
- # 25
host_id: 0
supervisor_host_id: 0
- # 26
host_id: 0
supervisor_host_id: 0
- # 27
host_id: 0
supervisor_host_id: 0
- # 28
host_id: 0
supervisor_host_id: 0
- # 29
host_id: 0
supervisor_host_id: 0
- # 30
host_id: 0
supervisor_host_id: 0
- # 31
host_id: 0
supervisor_host_id: 0
- # 32
host_id: 0
supervisor_host_id: 0
otp_config:
subhdr:
magic: 0x4081
size: 69
write_host_id: 0
otp_entry:
- # 1
host_id: 0
host_perms: 0
- # 2
host_id: 0
host_perms: 0
- # 3
host_id: 0
host_perms: 0
- # 4
host_id: 0
host_perms: 0
- # 5
host_id: 0
host_perms: 0
- # 6
host_id: 0
host_perms: 0
- # 7
host_id: 0
host_perms: 0
- # 8
host_id: 0
host_perms: 0
- # 9
host_id: 0
host_perms: 0
- # 10
host_id: 0
host_perms: 0
- # 11
host_id: 0
host_perms: 0
- # 12
host_id: 0
host_perms: 0
- # 13
host_id: 0
host_perms: 0
- # 14
host_id: 0
host_perms: 0
- # 15
host_id: 0
host_perms: 0
- # 16
host_id: 0
host_perms: 0
- # 17
host_id: 0
host_perms: 0
- # 18
host_id: 0
host_perms: 0
- # 19
host_id: 0
host_perms: 0
- # 20
host_id: 0
host_perms: 0
- # 21
host_id: 0
host_perms: 0
- # 22
host_id: 0
host_perms: 0
- # 23
host_id: 0
host_perms: 0
- # 24
host_id: 0
host_perms: 0
- # 25
host_id: 0
host_perms: 0
- # 26
host_id: 0
host_perms: 0
- # 27
host_id: 0
host_perms: 0
- # 28
host_id: 0
host_perms: 0
- # 29
host_id: 0
host_perms: 0
- # 30
host_id: 0
host_perms: 0
- # 31
host_id: 0
host_perms: 0
- # 32
host_id: 0
host_perms: 0
dkek_config:
subhdr:
magic: 0x5170
size: 12
allowed_hosts: [128, 0, 0, 0]
allow_dkek_export_tisci: 0x5A
rsvd: [0, 0, 0]
sa2ul_cfg:
subhdr:
magic: 0x23BE
size: 0
auth_resource_owner: 0
enable_saul_psil_global_config_writes: 0x5A
rsvd: [0, 0]
sec_dbg_config:
subhdr:
magic: 0x42AF
size: 16
allow_jtag_unlock: 0x5A
allow_wildcard_unlock: 0x5A
allowed_debug_level_rsvd: 0
rsvd: 0
min_cert_rev: 0x0
jtag_unlock_hosts: [0, 0, 0, 0]
sec_handover_cfg:
subhdr:
magic: 0x608F
size: 10
handover_msg_sender: 0
handover_to_host_id: 0
rsvd: [0, 0, 0, 0]

903
board/phytec/phycore_am62ax/tifs-rm-cfg.yaml Normal file
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@ -0,0 +1,903 @@
# SPDX-License-Identifier: GPL-2.0+
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
#
# Resource management configuration for AM62AX
#
---
tifs-rm-cfg:
rm_boardcfg:
rev:
boardcfg_abi_maj: 0x0
boardcfg_abi_min: 0x1
host_cfg:
subhdr:
magic: 0x4C41
size: 356
host_cfg_entries:
- # 1
host_id: 12
allowed_atype: 0x2A
allowed_qos: 0xAAAA
allowed_orderid: 0xAAAAAAAA
allowed_priority: 0xAAAA
allowed_sched_priority: 0xAA
- # 2
host_id: 30
allowed_atype: 0x2A
allowed_qos: 0xAAAA
allowed_orderid: 0xAAAAAAAA
allowed_priority: 0xAAAA
allowed_sched_priority: 0xAA
- # 3
host_id: 36
allowed_atype: 0x2A
allowed_qos: 0xAAAA
allowed_orderid: 0xAAAAAAAA
allowed_priority: 0xAAAA
allowed_sched_priority: 0xAA
- # 4
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 5
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 6
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 7
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 8
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 9
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 10
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 11
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 12
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 13
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 14
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 15
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 16
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 17
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 18
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 19
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 20
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 21
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 22
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 23
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 24
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 25
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 26
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 27
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 28
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 29
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 30
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 31
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
- # 32
host_id: 0
allowed_atype: 0
allowed_qos: 0
allowed_orderid: 0
allowed_priority: 0
allowed_sched_priority: 0
resasg:
subhdr:
magic: 0x7B25
size: 8
resasg_entries_size: 872
reserved: 0
resasg_entries:
-
start_resource: 0
num_resource: 18
type: 1677
host_id: 12
reserved: 0
-
start_resource: 18
num_resource: 6
type: 1677
host_id: 35
reserved: 0
-
start_resource: 18
num_resource: 6
type: 1677
host_id: 36
reserved: 0
-
start_resource: 24
num_resource: 2
type: 1677
host_id: 30
reserved: 0
-
start_resource: 26
num_resource: 6
type: 1677
host_id: 128
reserved: 0
-
start_resource: 54
num_resource: 18
type: 1678
host_id: 12
reserved: 0
-
start_resource: 72
num_resource: 6
type: 1678
host_id: 35
reserved: 0
-
start_resource: 72
num_resource: 6
type: 1678
host_id: 36
reserved: 0
-
start_resource: 78
num_resource: 2
type: 1678
host_id: 30
reserved: 0
-
start_resource: 80
num_resource: 2
type: 1678
host_id: 128
reserved: 0
-
start_resource: 32
num_resource: 12
type: 1679
host_id: 12
reserved: 0
-
start_resource: 44
num_resource: 6
type: 1679
host_id: 35
reserved: 0
-
start_resource: 44
num_resource: 6
type: 1679
host_id: 36
reserved: 0
-
start_resource: 50
num_resource: 2
type: 1679
host_id: 30
reserved: 0
-
start_resource: 52
num_resource: 2
type: 1679
host_id: 128
reserved: 0
-
start_resource: 0
num_resource: 18
type: 1696
host_id: 12
reserved: 0
-
start_resource: 18
num_resource: 6
type: 1696
host_id: 35
reserved: 0
-
start_resource: 18
num_resource: 6
type: 1696
host_id: 36
reserved: 0
-
start_resource: 24
num_resource: 2
type: 1696
host_id: 30
reserved: 0
-
start_resource: 26
num_resource: 6
type: 1696
host_id: 128
reserved: 0
-
start_resource: 0
num_resource: 18
type: 1697
host_id: 12
reserved: 0
-
start_resource: 18
num_resource: 6
type: 1697
host_id: 35
reserved: 0
-
start_resource: 18
num_resource: 6
type: 1697
host_id: 36
reserved: 0
-
start_resource: 24
num_resource: 2
type: 1697
host_id: 30
reserved: 0
-
start_resource: 26
num_resource: 2
type: 1697
host_id: 128
reserved: 0
-
start_resource: 0
num_resource: 12
type: 1698
host_id: 12
reserved: 0
-
start_resource: 12
num_resource: 6
type: 1698
host_id: 35
reserved: 0
-
start_resource: 12
num_resource: 6
type: 1698
host_id: 36
reserved: 0
-
start_resource: 18
num_resource: 2
type: 1698
host_id: 30
reserved: 0
-
start_resource: 20
num_resource: 2
type: 1698
host_id: 128
reserved: 0
-
start_resource: 6
num_resource: 34
type: 1802
host_id: 12
reserved: 0
-
start_resource: 44
num_resource: 36
type: 1802
host_id: 35
reserved: 0
-
start_resource: 44
num_resource: 36
type: 1802
host_id: 36
reserved: 0
-
start_resource: 168
num_resource: 8
type: 1802
host_id: 30
reserved: 0
-
start_resource: 0
num_resource: 1024
type: 1807
host_id: 128
reserved: 0
-
start_resource: 4096
num_resource: 29
type: 1808
host_id: 128
reserved: 0
-
start_resource: 4608
num_resource: 99
type: 1809
host_id: 128
reserved: 0
-
start_resource: 5120
num_resource: 24
type: 1810
host_id: 128
reserved: 0
-
start_resource: 5632
num_resource: 51
type: 1811
host_id: 128
reserved: 0
-
start_resource: 6144
num_resource: 51
type: 1812
host_id: 128
reserved: 0
-
start_resource: 6656
num_resource: 51
type: 1813
host_id: 128
reserved: 0
-
start_resource: 8192
num_resource: 32
type: 1814
host_id: 128
reserved: 0
-
start_resource: 8704
num_resource: 32
type: 1815
host_id: 128
reserved: 0
-
start_resource: 9216
num_resource: 32
type: 1816
host_id: 128
reserved: 0
-
start_resource: 9728
num_resource: 22
type: 1817
host_id: 128
reserved: 0
-
start_resource: 10240
num_resource: 22
type: 1818
host_id: 128
reserved: 0
-
start_resource: 10752
num_resource: 22
type: 1819
host_id: 128
reserved: 0
-
start_resource: 11264
num_resource: 28
type: 1820
host_id: 128
reserved: 0
-
start_resource: 11776
num_resource: 28
type: 1821
host_id: 128
reserved: 0
-
start_resource: 12288
num_resource: 28
type: 1822
host_id: 128
reserved: 0
-
start_resource: 0
num_resource: 10
type: 1936
host_id: 12
reserved: 0
-
start_resource: 10
num_resource: 3
type: 1936
host_id: 35
reserved: 0
-
start_resource: 10
num_resource: 3
type: 1936
host_id: 36
reserved: 0
-
start_resource: 13
num_resource: 3
type: 1936
host_id: 30
reserved: 0
-
start_resource: 16
num_resource: 3
type: 1936
host_id: 128
reserved: 0
-
start_resource: 19
num_resource: 64
type: 1937
host_id: 12
reserved: 0
-
start_resource: 19
num_resource: 64
type: 1937
host_id: 30
reserved: 0
-
start_resource: 83
num_resource: 8
type: 1938
host_id: 12
reserved: 0
-
start_resource: 91
num_resource: 8
type: 1939
host_id: 12
reserved: 0
-
start_resource: 99
num_resource: 10
type: 1942
host_id: 12
reserved: 0
-
start_resource: 109
num_resource: 3
type: 1942
host_id: 35
reserved: 0
-
start_resource: 109
num_resource: 3
type: 1942
host_id: 36
reserved: 0
-
start_resource: 112
num_resource: 3
type: 1942
host_id: 30
reserved: 0
-
start_resource: 115
num_resource: 3
type: 1942
host_id: 128
reserved: 0
-
start_resource: 118
num_resource: 16
type: 1943
host_id: 12
reserved: 0
-
start_resource: 118
num_resource: 16
type: 1943
host_id: 30
reserved: 0
-
start_resource: 134
num_resource: 8
type: 1944
host_id: 12
reserved: 0
-
start_resource: 134
num_resource: 8
type: 1945
host_id: 12
reserved: 0
-
start_resource: 142
num_resource: 8
type: 1946
host_id: 12
reserved: 0
-
start_resource: 142
num_resource: 8
type: 1947
host_id: 12
reserved: 0
-
start_resource: 0
num_resource: 10
type: 1955
host_id: 12
reserved: 0
-
start_resource: 10
num_resource: 3
type: 1955
host_id: 35
reserved: 0
-
start_resource: 10
num_resource: 3
type: 1955
host_id: 36
reserved: 0
-
start_resource: 13
num_resource: 3
type: 1955
host_id: 30
reserved: 0
-
start_resource: 16
num_resource: 3
type: 1955
host_id: 128
reserved: 0
-
start_resource: 19
num_resource: 8
type: 1956
host_id: 12
reserved: 0
-
start_resource: 19
num_resource: 8
type: 1956
host_id: 30
reserved: 0
-
start_resource: 27
num_resource: 1
type: 1957
host_id: 12
reserved: 0
-
start_resource: 28
num_resource: 1
type: 1958
host_id: 12
reserved: 0
-
start_resource: 0
num_resource: 10
type: 1961
host_id: 12
reserved: 0
-
start_resource: 10
num_resource: 3
type: 1961
host_id: 35
reserved: 0
-
start_resource: 10
num_resource: 3
type: 1961
host_id: 36
reserved: 0
-
start_resource: 13
num_resource: 3
type: 1961
host_id: 30
reserved: 0
-
start_resource: 16
num_resource: 3
type: 1961
host_id: 128
reserved: 0
-
start_resource: 0
num_resource: 10
type: 1962
host_id: 12
reserved: 0
-
start_resource: 10
num_resource: 3
type: 1962
host_id: 35
reserved: 0
-
start_resource: 10
num_resource: 3
type: 1962
host_id: 36
reserved: 0
-
start_resource: 13
num_resource: 3
type: 1962
host_id: 30
reserved: 0
-
start_resource: 16
num_resource: 3
type: 1962
host_id: 128
reserved: 0
-
start_resource: 19
num_resource: 1
type: 1963
host_id: 12
reserved: 0
-
start_resource: 19
num_resource: 1
type: 1963
host_id: 30
reserved: 0
-
start_resource: 19
num_resource: 16
type: 1964
host_id: 12
reserved: 0
-
start_resource: 19
num_resource: 16
type: 1964
host_id: 30
reserved: 0
-
start_resource: 20
num_resource: 1
type: 1965
host_id: 12
reserved: 0
-
start_resource: 35
num_resource: 8
type: 1966
host_id: 12
reserved: 0
-
start_resource: 21
num_resource: 1
type: 1967
host_id: 12
reserved: 0
-
start_resource: 35
num_resource: 8
type: 1968
host_id: 12
reserved: 0
-
start_resource: 22
num_resource: 1
type: 1969
host_id: 12
reserved: 0
-
start_resource: 43
num_resource: 8
type: 1970
host_id: 12
reserved: 0
-
start_resource: 23
num_resource: 1
type: 1971
host_id: 12
reserved: 0
-
start_resource: 43
num_resource: 8
type: 1972
host_id: 12
reserved: 0
-
start_resource: 0
num_resource: 1
type: 2112
host_id: 128
reserved: 0
-
start_resource: 2
num_resource: 2
type: 2122
host_id: 12
reserved: 0
-
start_resource: 0
num_resource: 6
type: 12750
host_id: 12
reserved: 0
-
start_resource: 0
num_resource: 6
type: 12769
host_id: 12
reserved: 0
-
start_resource: 0
num_resource: 8
type: 12810
host_id: 12
reserved: 0
-
start_resource: 3072
num_resource: 6
type: 12828
host_id: 128
reserved: 0
-
start_resource: 3584
num_resource: 6
type: 12829
host_id: 128
reserved: 0
-
start_resource: 4096
num_resource: 6
type: 12830
host_id: 128
reserved: 0

181
configs/phycore_am62ax_a53_defconfig Normal file
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@ -0,0 +1,181 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM62A7=y
CONFIG_PHYTEC_SOM_DETECTION=y
CONFIG_PHYTEC_SOM_DETECTION_BLOCKS=y
CONFIG_TARGET_PHYCORE_AM62AX_A53=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62a7-phyboard-lyra-rdk"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_STACK_R=y
CONFIG_ENV_OFFSET_REDUND=0x6c0000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_BOOTSTD_FULL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run ${boot}boot; bootflow scan -lb"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NET=y
CONFIG_SPL_NET_VCI_STRING="AM62AX U-Boot A53 SPL"
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_DEVICE=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_RTC=y
CONFIG_CMD_SMC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_FIXED=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPL_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_REMOTEPROC_TI_K3_DSP=y
CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_RTC=y
CONFIG_RTC_RV3028=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_SPL_USB_HOST=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_SPL_USB_DWC3_GENERIC=y
CONFIG_SPL_USB_DWC3_AM62=y
CONFIG_USB_DWC3_AM62=y
CONFIG_SPL_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
CONFIG_SPL_DFU=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384

129
configs/phycore_am62ax_r5_defconfig Normal file
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@ -0,0 +1,129 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_F_LEN=0x9000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SOC_K3_AM62A7=y
CONFIG_TARGET_PHYCORE_AM62AX_R5=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x680000
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-r5-phycore-som-2gb"
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x7145
CONFIG_SPL_TEXT_BASE=0x43c00000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x43c3b000
CONFIG_SPL_BSS_MAX_SIZE=0x3000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SIZE_LIMIT=0x3A7F0
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x3500
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
CONFIG_SPL_MAX_SIZE=0x3B000
CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SPL_DMA=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_REMOTEPROC=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SPL_THERMAL=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_SPL_DM=y
CONFIG_SPL_DM_DEVICE_REMOVE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SPL_CLK_CCF=y
CONFIG_SPL_CLK_K3_PLL=y
CONFIG_SPL_CLK_K3=y
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
# CONFIG_GPIO is not set
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_ESM_K3=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_POWER_DOMAIN=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_RESET_TI_SCI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_LIB_RATIONAL=y
CONFIG_SPL_LIB_RATIONAL=y

15
include/configs/phycore_am62ax.h Normal file
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@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
/*
* Configuration header file for PHYTEC phyCORE-AM62Ax
*
* Copyright (C) 2024 PHYTEC America LLC
* Author: Garrett Giordano <ggiordano@phytec.com>
*/
#ifndef __PHYCORE_AM62AX_H
#define __PHYCORE_AM62AX_H
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE 0x80000000
#endif /* __PHYCORE_AM62AX_H */