Commit graph

97786 commits

Author SHA1 Message Date
Liya Huang
5cf9e61f0f examples: fix building on arm32
Refer to the commit a3c101a613 ("examples: fix building on arm64")
fix for arm32. crt0.S does not even build with:
    operating system and architecture:
        5.15.0-130-generic x86_64
    installed version of gcc and binutils:
        gcc version 9.4.0 (Ubuntu 9.4.0-1ubuntu1~20.04.3)
    GNU ld (GNU Binutils for Ubuntu) 2.34
    used defconfig:
        stm32h750-art-pi_defconfig
    used commands for building:
        export CROSS_COMPILE=arm-none-eabi- ARCH=arm
        make stm32h750-art-pi_defconfig
        make menuconfig # to add
        make
    examples/api/crt0.S: Assembler messages:
    examples/api/crt0.S:32: Error: lo register required -- `ldr ip,=search_hint'
    examples/api/crt0.S:33: Error: lo register required -- `str sp,[ip]'
    examples/api/crt0.S:39: Error: lo register required -- `ldr ip,=syscall_ptr'
    examples/api/crt0.S:40: Error: lo register required -- `ldr pc,[ip]'
    make[2]: *** [scripts/Makefile.build:292:examples/api/crt0.o] Error 1

Use valid register names and instructions.

Signed-off-by: Liya Huang <1425075683@qq.com>
2025-02-04 11:57:36 -06:00
Liya Huang
adeea8568d API: system info adds FLASH and clk fetches
Refer to api/api platform-powerpc.c implementation

Signed-off-by: Liya Huang <1425075683@qq.com>
2025-02-04 11:57:36 -06:00
Heinrich Schuchardt
72bbb645b3 examples: eliminate CONFIG_STANDALONE_LOAD_ADDR
CONFIG_STANDALONE_LOAD_ADDR has been used for examples/standalone
but not for examples/api.

The suitability of an address to load an ELF binary and run it does
not only depend on the architecture but also on the memory layout of
the board which is not reflected in the default value of
CONFIG_STANDALONE_LOAD_ADDR.

Commit 32b7e39db4 ("Convert CONFIG_STANDALONE_LOAD_ADDR to Kconfig")
set the default on RISC-V to 0x0 though most boards used 0x80200000
before the patch.

On most boards we can assume 8 MiB of memory available above $loadaddr.
So we can safely use $loadaddr + 4 MiB as load address for the standalone
example and eliminate CONFIG_STANDALONE_LOAD_ADDR altogether.

Fixes: 32b7e39db4 ("Convert CONFIG_STANDALONE_LOAD_ADDR to Kconfig")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-02-04 11:57:36 -06:00
Heinrich Schuchardt
1df9cbd70f examples/api: improve determination of LOAD_ADDR
The current load address for the 'demo' binary does not work for
qemu_arm_defconfig.

The suitability of an address to load an ELF binary and run it does
not only depend on the architecture but also on the memory layout of
the board.

On most boards we can assume that 8 MiB of memory is available above
$loadaddr. So $loadaddr + 0x400000 should work there.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-02-04 11:57:36 -06:00
Quentin Schulz
881f0b77dc image: apply FDTOs on FDT image node without a load property
A FIT image which is NOT using -E when created by mkimage - that is with
image data within the FIT - will fail to apply FDTO if the base FDT
image node does not specify a load property (which points to an address
in DRAM). This is because we check that the FDT address we want to apply
overlay to (i.e. modify and likely increase in size) is not inside the
FIT and give up otherwise. This is assumed necessary because we may then
overwrite other data when applying in-place.

However, we can do better than giving up: relocating the FDT in another
place in DRAM where it's safe to increase its size and apply FDTOs.

While at it, do not discriminate anymore on whether the data is within
the FIT data address space - that is FIT images created with mkimage -E
- as that still may be susceptible to unintended data overwrites as
mkimage -E simply concatenates all blobs after the FIT. If the FDT blob
isn't the last, it'll result in overwriting later blobs when resizing.

The side effect is that the load property in the FIT is only
temporarily used to load the FDT but then relocated right before we
start applying overlays.

Suggested-by: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-02-04 11:57:36 -06:00
Tom Rini
bfaed6969c Merge patch series "mediatek: final preparation for OF_UPSTREAM support"
Christian Marangi <ansuelsmth@gmail.com> says:

This is the last batch of part to push actual support of
OF_UPSTREAM for the mediatek SoC.

The plan is to make the current downstream DTS on part with
upstream implementation so we can permit a gradual transition to
it while we don't cause any regression to any user.

This is to have the same node downstream and upstream.
Mediatek is working hard upstream to also push all the remaining
nodes.

All patch are the final changes after the pinctrl patch
merged previously.

All patch pass CI tests

Link: https://github.com/u-boot/u-boot/pull/731
Link: https://lore.kernel.org/r/20250127134046.26345-1-ansuelsmth@gmail.com
2025-02-04 11:57:36 -06:00
Christian Marangi
c6f8119dc4 arm: dts: mediatek: add PCIe node for MT7981
Add PCIe node for MT7981 with all the required properties to make PCIe
work.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-04 10:20:36 -06:00
John Crispin
5fa18e47e4 arm: dts: mediatek: add USB nodes for MT7981
Add USB PHY nodes for MT7981. These are needed for USB support and also
for PCIe support as the u3 PHY can also be used for PHY.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-04 10:20:36 -06:00
Christian Marangi
4d173d4a64 mediatek: mt7981: move gpio-controller up and rename pinctrl to pio
Move gpio-controller up to pinctrl node and rename label to "pio" to
match the label used in upstream kernel linux.

Update any DTS that reference the pinctrl to follow the new naming and
structure.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-04 10:20:36 -06:00
Christian Marangi
cd06e60c44 mediatek: mt7988: move gpio-controller up and rename pinctrl to pio
Move gpio-controller up to pinctrl node and rename label to "pio" to
match the label used in upstream kernel linux.

Update any DTS that reference the pinctrl to follow the new naming and
structure.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-04 10:20:36 -06:00
Christian Marangi
8c2cb748ef pinctrl: mediatek: mt7988: rename reg-names to upstream linux format
Rename reg-names to upstream linux format. Upstream linux drop the
"_base". To make use of upstream DTSI, align to the upstream naming.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-04 10:20:36 -06:00
Christian Marangi
f1775996ba mediatek: mt7986: move gpio-controller up and rename pinctrl to pio
Move gpio-controller up to pinctrl node and rename label to "pio" to
match the label used in upstream kernel linux.

Update any DTS that reference the pinctrl to follow the new naming and
structure.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-04 10:20:36 -06:00
Christian Marangi
08e70f772c pinctrl: mediatek: mt7986: rename reg-names to upstream linux format
Rename reg-names to upstream linux format. Upstream linux drop the
"_base". To make use of upstream DTSI, align to the upstream naming.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-04 10:20:36 -06:00
Christian Marangi
8b1ea8a4b9 pinctrl: mediatek: mt7981: rename reg-names to upstream linux format
Rename reg-names to upstream linux format. Upstream linux drop the
"_base". To make use of upstream DTSI, align to the upstream naming.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-04 10:20:36 -06:00
Tom Rini
3e69c75e86 Merge patch series "vbe: Series part G"
Simon Glass <sjg@chromium.org> says:

This includes the VBE ABrec (A/B/recovery) implementation as well as a
number of patches needed to make it work:

- marking some code as used by SPL_RELOC
- selection of images from a FIT based on the boot phase
- removal of unwanted hash code which increases code-size too much
- a few Kconfig-related additions for VPL

Note: The goal for the next series (part H) is to enable VBE on
rk3399-generic, i.e. able to boot on multiple rk3399-based boards with
only the TPL phase being different for each board.

Link: https://lore.kernel.org/r/20250126184333.4058848-1-sjg@chromium.org/
2025-02-03 16:01:44 -06:00
Simon Glass
f1eb367d76 vbe: Add an implementation of VBE-ABrec
So far only VBE-simple is implemented in U-Boot. This supports a single
image which can be updated in situ.

It is often necessary to support two images (A and B) so that the board
is not bricked if the update is interrupted or is bad.

In some cases, a non-updatable recovery image is desirable, so that the
board can be returned to a known-good state in the event of a serious
failure.

Introduce ABrec which provides these features. It supports three
independent images and the logic to select the desired one on boot.

While we are here, fix a debug message to indicate the function it
called. Provide a maintainers entry for VBE.

Note that fwupdated only supports VBE-simple so far, but supports for
ABrec will appear in time.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-03 16:01:36 -06:00
Simon Glass
f4415f2a37 vbe: Allow VBE to disable adding loadables to the FDT
When VBE operates within VPL it does not want the FDT to be changed.
Provide a way to disable this feature.

Move the FIT_IMAGE_TINY condition out of spl_fit_record_loadable() so
that both conditions are together. This makes the code easier to
understand.

Replace the existing fit_loaded member, which is no-longer used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-03 16:01:36 -06:00
Simon Glass
39a9b033ce vbe: Tidy up a few comments
Join the comment block for the fit_image_load() call back to where it
should be. Also fix a debug statement.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-03 16:01:36 -06:00
Simon Glass
dab3bbc2b8 vbe: Provide VPL binman-symbols for the next phase
Add support for moving from TPL->VPL->SPL so that the VPL build can fit
properly into the boot flow.

Use #ifdefs to avoid creating unwanted symbols which Binman would then
try (and perhaps fail) to provide.

Add debugging to indicate the next phase.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-03 16:01:36 -06:00
Simon Glass
384f815d08 vbe: Support providing a linker script
Allow a linker script to be provided for VPL as it is for other U-Boot
phases.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-03 16:01:36 -06:00
Simon Glass
5c751dc091 lib: Mark gunzip as relocation code
Mark the gunzip code as needed by relocation. This is used to decompress
the next-phase image.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-03 16:01:36 -06:00
Simon Glass
4ca2970390 lib: Mark memcpy() and memmove() as relocation code
Mark these functions as needed by relocation. These functions are used
to copy data while relocating the next-phase image.

Drop the 'safe' versions from SPL as they are not needed. Change the
static array to a local one, to avoid link errors when trying to access
the data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-03 16:01:36 -06:00
Simon Glass
6e5b3d4265 lib: Mark lz4 as relocation code
Mark the lz4 decompression code as needed by relocation. This is used to
decompress the next-phase image.

Drop the 'safe' versions from SPL as they are not needed. Change the
static array to a local one, to avoid a crash errors when trying to
access the data from relocated code. Make this conditional to avoid a
code-size increase when SPL_RELOC is not used/

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-03 16:01:36 -06:00
Simon Glass
3b52337c75 lib: Mark crc8 as relocation code
Mark the crc8 code as needed by relocation. This is used as a simple
check against corruption of the code when copying.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-03 16:01:36 -06:00
Simon Glass
0741165f3f spl: Provide a way to mark code needed for relocation
Add a linker symbol which can be used to mark relocation code, so it can
be collected by the linker and copied into a suitable place and executed
when needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-03 16:01:36 -06:00
Simon Glass
fe71ebbea9 spl: Allow spl_load() to be controlled in any xPL phase
Some phases may wish to use full FIT-loading and others not, so allow
this to be controlled.

Add some debugging while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-03 16:01:36 -06:00
Simon Glass
5fb647c83e vbe: Support selecting images based on phase in FIT
With SPL we want to specify the phase of the image to be loaded. Add
support for this.

This is the implementation of a FIT feature added to the spec a few
years ago and entails a small code-size increase, about 70 bytes on
Thumb2.

Signed-off-by: Simon Glass <sjg@chromium.org>
Link: https://docs.u-boot.org/en/latest/usage/fit/index.html
2025-02-03 16:01:36 -06:00
Simon Glass
873112db9c spl: Support selecting images based on phase in simple FIT
At present the simple FIT-loader always loads images, ignoring whether
they are intended for the next phase or not.

VBE packages up several images in the same FIT, some destined for VPL
and some for SPL. Add logic to check the phase before loading the
image. Return -EPERM in that case and handle it gracefully.

Fix a unnecessary re-computation of read_offset while here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-03 16:01:36 -06:00
Simon Glass
c38b372f35 spl: Avoid including hash algorithms which are not wanted
Update the build rule so that hash algorithms are only included in an
SPL build if they are requested. This helps to reduce code size.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-02-03 16:01:36 -06:00
Simon Glass
b0407ace97 spl: Adjust debugging and xPL symbols
The size of some malloc() fields has reduced on 64-bit machines, but
the spl_reloc code was not updated. Fix this to avoid a compiler
warning.

Also update for the new xPL naming.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-02-03 16:00:42 -06:00
Simon Glass
5929c2f39f lib: Allow crc16 code to be dropped
This code is not necessarily needed in VPL, even if SPL uses it, so
adjust the rules to allow it to be dropped.

Do the same for the hash API.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-02-03 16:00:42 -06:00
Simon Glass
00ae9b2ac3 mmc: Allow controlling DM_MMC for VPL builds
VPL may want to use driver model for MMC even if TPL does not. Update
the rule in this driver to support that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-02-03 16:00:42 -06:00
Simon Glass
4acbd003d3 sandbox: Update sandbox_vpl to select sha1 and sha256
These algorithms are used in VPL, so enable them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-03 16:00:42 -06:00
Simon Glass
117e7cb9f8 mbedtls: Add SHA symbols for VPL
Add some symbols for supporting SHA1 etc. for VPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-03 16:00:42 -06:00
Tom Rini
752321b625 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/24428

- RISC-V: Add some fixes
- RISC-V: Integrate OP-TEE into the RISC-V boot flow
- RISC-V: Unify implementation of cleanup_before_linux() for RISC-V
  ports
- RISC-V: cmd: Add bhyve SBI implementation ID
- Board: K1: Probe dram size during boot phase
2025-02-03 08:24:49 -06:00
Yao Zi
faf237d1b4 riscv: cpu: jh7110: fallback to generic cleanup_before_linux()
JH7110 SoC requires no specific handling before entering Linux kernel.
Let's drop the specific implementation to avoid duplication.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 15:26:06 +08:00
Yao Zi
334980f4cf riscv: cpu: generic: fallback to generic cleanup_before_linux()
The current implementation is equivalent to the fallback one, so
this shouldn't change any behaviour but cleans the code up only.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 15:26:06 +08:00
Yao Zi
f88e3b7739 riscv: add a generic implementation for cleanup_before_linux()
Most RISC-V SoCs have similar cleanup_before_linux() functions. Let's
provide a weak symbol as fallback to reduce duplicated code.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 15:26:06 +08:00
Yu-Chien Peter Lin
47d90f6bd3 riscv: dts: binman.dtsi: Include OP-TEE OS image
The following diagram illustrates the boot flow for OP-TEE OS
initialization on RISC-V.

    (1)-----------+
     | U-Boot SPL |
     +------------+
         |
         v
    (2)-------------------------------------------------------------+
     | OpenSBI (fw_dynamic.bin)                                     |
     |                (4)------------------------+                  |
     |                 | optee dispatcher driver |                  |
     +-----------------+-------^---------|-------+------------------+
M-mode   |                     |         |
---------+--[trusted domain]---+----.----+--[untrusted domain]-------
S-mode   |  (coldboot domain)  |    |    |
         v                     |    |    v
    (3)---------------------------+ |(5)----------------------------+
     | OP-TEE OS (tee.bin)        | | | U-Boot (u-boot-nodtb.bin)   |
     +----------------------------+ | +-----------------------------+
                                    |    |
                                    |    v
                                    |(6)----------------------------+
                                    | | Linux                       |
                                    | +-----------------------------+

This patch enables the inclusion of the OP-TEE binary within the
U-Boot ITB, allowing it to be loaded to a platform defined address
by U-Boot SPL.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 15:26:00 +08:00
Yu-Chien Peter Lin
99654e1b96 riscv: Add CONFIG_SPL_OPTEE_LOAD_ADDR
Allow specifying load address of OP-TEE binary. It is
recommended that the specified address aligns with the
base address of an PMP-protected NAPOT region and matches
the CFG_TDDRAM_START configuration in OP-TEE.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 15:26:00 +08:00
Heinrich Schuchardt
ca3985ff86 cmd: sbi: add bhyve SBI implementation ID
Bhyve is the hypervisor used by FreeBSD.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 11:33:04 +08:00
Heinrich Schuchardt
490be9de22 riscv: AVAILABLE_HARTS is not compatible with XIP
If CONFIG_AVAILABLE_HARTS=y, variable available_harts_lock is created in
the data section which will not be writable while executing from flash.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 11:33:04 +08:00
Huan Zhou
3691fbccfc riscv: spacemit: k1: probe dram size during boot phase.
Implement functionality to probe and calculate the DRAM size
during the boot phase for the RISC-V spacemit K1 platform.

Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # BPI-F3 16G
Signed-off-by: Huan Zhou <me@per1cycle.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 11:33:04 +08:00
Hal Feng
b6d150b949 pinctrl: starfive: Correct driver declaration for starfive_gpio
Use the driver macros so that the driver appears in the
linker list.

Reported-by: Simon Glass <sjg@chromium.org>
Fixes: 732f01aabf ("pinctrl: starfive: Add StarFive JH7110 driver")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
2025-02-03 11:33:04 +08:00
Michal Simek
2b1c8d3b2d cmd: Fix Kconfig coding style
Some entries are not using tabs for indentation and also help should use
two spaces indentation.

Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-01-31 11:29:05 -06:00
Weijie Gao
7f95b5d7e6 net: mediatek: fix coding style of AN8855 switch driver
This patch fixed the following coding style suggested by checkpatch.pl:
1. Use tab instead of space
2. Use BIT() instead of <<
3. Use mdelay for long time delay
4. Remove useless parenthesises

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-31 11:29:01 -06:00
Weijie Gao
ea02a07728 pinctrl: mediatek: update mt7981 pinctrl driver based on upstream kernel
Update mt7981 pinctrl driver based on upstream kernel

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-31 11:28:59 -06:00
Neil Armstrong
664a257777 scsi: do not fill the LUN in the second CDB byte
The SCSI specification originally required that the second
Command Data Byte contain the LUN value in its high-order bits,
but this field has been marked as reserved since the SCSI-3 spec
from 1996.

Some vendors uses this byte to pass vendor specific data,
and specifying the LUN can trigger strange behaviors.
For the record, this happened on an UFS device where LUN0 was
working perfectly and reading the other LUNs would get the last
buffer data that was read for LUN0, making this issue very very
hard to debug.

It's sane to assume U-Boot will probably never encounter
an SCSI-2 multi-LUN device, if somehow it happens the enquiry
command would need to get the SCSI level to handle this case.

The Linux fix was added in [1] to fix the exact same issue.

[1] https://lore.kernel.org/all/Pine.LNX.4.44L0.1409021108380.2308-100000@iolanthe.rowland.org/

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-01-31 11:28:55 -06:00
Daniel Schultz
058ed281fa board: phytec: common: k3: Expose product infos to Linux
Call 'phytec_ft_board_fixup' in the common K3 board code
to expose the product name and part number to Linux.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
2025-01-31 11:08:04 -06:00
Daniel Schultz
9c46b8c4e0 board: phytec: common: Add product information to FTD
ft_board_setup inside the board code allows to alter
device-tree during the boot process.

Introduce a new function for the PHYTEC SOM detection
to read the product name and part number from the EEPROM
content and include both into the device-tree as
* phytec,som-part-number
* phytec,som-product-name

This function can be called from the board code when those
values should be exposed to Linux.

This patch also updates the phytec_print_som_info
function and changes the output.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
2025-01-31 11:08:04 -06:00