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Merge patch series "api: Remove duplicate newlines"

Browse source 
This removes a number of duplicate newlines throughout the codebase.
This commit is contained in:
Tom Rini 2024-07-15 12:28:22 -06:00
commit af3c2166d5
363 changed files with 0 additions and 1101 deletions
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6
api/api.c
View file

@ -180,7 +180,6 @@ static int API_get_timer(va_list ap)
return 0;
}
/*****************************************************************************
*
* pseudo signature:
@ -230,7 +229,6 @@ static int API_dev_enum(va_list ap)
return 0;
}
static int API_dev_open(va_list ap)
{
struct device_info *di;
@ -262,7 +260,6 @@ static int API_dev_open(va_list ap)
return err;
}
static int API_dev_close(va_list ap)
{
struct device_info *di;
@ -297,7 +294,6 @@ static int API_dev_close(va_list ap)
return err;
}
/*
* pseudo signature:
*
@ -376,7 +372,6 @@ static int API_dev_write(va_list ap)
return err;
}
/*
* pseudo signature:
*
@ -462,7 +457,6 @@ static int API_dev_read(va_list ap)
return 0;
}
/*
* pseudo signature:
*

8
api/api_storage.c
View file

@ -26,7 +26,6 @@
#define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0)
#define ENUM_IDE 0
#define ENUM_USB 1
#define ENUM_SCSI 2
@ -144,7 +143,6 @@ static int dev_stor_get(int type, int *more, struct device_info *di)
return found;
}
/* returns: ENUM_IDE, ENUM_USB etc. based on struct blk_desc */
static int dev_stor_type(struct blk_desc *dd)
@ -159,7 +157,6 @@ static int dev_stor_type(struct blk_desc *dd)
return ENUM_MAX;
}
/* returns: 0/1 whether cookie points to some device in this group */
static int dev_is_stor(int type, struct device_info *di)
@ -167,7 +164,6 @@ static int dev_is_stor(int type, struct device_info *di)
return (dev_stor_type(di->cookie) == type) ? 1 : 0;
}
static int dev_enum_stor(int type, struct device_info *di)
{
int found = 0, more = 0;
@ -293,7 +289,6 @@ static int dev_stor_is_valid(int type, struct blk_desc *dd)
return 0;
}
int dev_open_stor(void *cookie)
{
int type = dev_stor_type(cookie);
@ -307,7 +302,6 @@ int dev_open_stor(void *cookie)
return API_ENODEV;
}
int dev_close_stor(void *cookie)
{
/*
@ -317,7 +311,6 @@ int dev_close_stor(void *cookie)
return 0;
}
lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start)
{
int type;
@ -341,7 +334,6 @@ lbasize_t dev_read_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start
#endif /* defined(CONFIG_BLK) */
}
lbasize_t dev_write_stor(void *cookie, void *buf, lbasize_t len, lbastart_t start)
{
struct blk_desc *dd = (struct blk_desc *)cookie;

2
arch/arc/include/asm/io.h
View file

@ -77,7 +77,6 @@ static inline void sync(void)
#define __arch_putl(v, a) ({ __comp_b(); *(volatile u32 *)(a) = (v); __comp_b(); })
#define __arch_putq(v, a) ({ __comp_b(); *(volatile u64 *)(a) = (v); __comp_b(); })
/*
* We add memory barriers for __raw_readX / __raw_writeX accessors same way as
* it is done for readX and writeX accessors as lots of U-Boot driver uses
@ -93,7 +92,6 @@ static inline void sync(void)
#define __raw_readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
#define __raw_readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; })
static inline void __raw_writesb(unsigned long addr, const void *data,
int bytelen)
{

1
arch/arm/cpu/arm926ejs/cpu.c
View file

@ -44,7 +44,6 @@ int cleanup_before_linux (void)
disable_interrupts();
/* turn off I/D-cache */
icache_disable();
dcache_disable();

1
arch/arm/cpu/armv7/arch_timer.c
View file

@ -49,7 +49,6 @@ unsigned long long get_ticks(void)
return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
}
ulong timer_get_boot_us(void)
{
if (!gd->arch.timer_rate_hz)

1
arch/arm/cpu/armv7/bcm235xx/clk-core.c
View file

@ -84,7 +84,6 @@ static int peri_clk_enable(struct clk *c, int enable)
struct bcm_clk_gate *gate = &cd->gate;
void *base = (void *)c->ccu_clk_mgr_base;
debug("%s: %s\n", __func__, c->name);
clk_get_rate(c); /* Make sure rate and sel are filled in */

1
arch/arm/cpu/armv7/bcm281xx/clk-core.c
View file

@ -84,7 +84,6 @@ static int peri_clk_enable(struct clk *c, int enable)
struct bcm_clk_gate *gate = &cd->gate;
void *base = (void *)c->ccu_clk_mgr_base;
debug("%s: %s\n", __func__, c->name);
clk_get_rate(c); /* Make sure rate and sel are filled in */

1
arch/arm/cpu/armv7/ls102xa/cpu.c
View file

@ -224,7 +224,6 @@ void enable_caches(void)
}
#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
uint get_svr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);

1
arch/arm/dts/vf610-pinfunc.h
View file

@ -20,7 +20,6 @@
#define ALT6 0x6
#define ALT7 0x7
#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0

1
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View file

@ -190,7 +190,6 @@
#define SCR0_CLIENTPD_MASK 0x00000001
#define SCR0_USFCFG_MASK 0x00000400
/* PCIe */
#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)

1
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
View file

@ -37,7 +37,6 @@
*
*/
#define FSL_INVALID_STREAM_ID 0
/* legacy devices */

1
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
View file

@ -97,7 +97,6 @@
#define FSL_PEX_STREAM_ID_END (0x100)
#endif
/* DPAA2 - set in MC DPC and alloced by MC */
#define FSL_DPAA2_STREAM_ID_START 23
#define FSL_DPAA2_STREAM_ID_END 63

1
arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h
View file

@ -49,5 +49,4 @@
#define USB2_PHY01_REFCLK_SEL (1 << 12)
#define USB2_PHY2_REFCLK_SEL (1 << 14)
#endif

2
arch/arm/include/asm/arch-hi6220/hi6220.h
View file

@ -133,7 +133,6 @@ struct peri_sc_periph_regs {
u32 reserved8_addr; /*0xd04*/
};
/* CTRL1 bit definitions */
#define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0)
@ -143,7 +142,6 @@ struct peri_sc_periph_regs {
#define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17)
#define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18)
/* CTRL2 bit definitions */
#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0)

1
arch/arm/include/asm/arch-hi6220/pinmux.h
View file

@ -9,7 +9,6 @@
#include "periph.h"
/* iomg bit definition */
#define MUX_M0 0
#define MUX_M1 1

1
arch/arm/include/asm/arch-lpc32xx/config.h
View file

@ -8,7 +8,6 @@
#ifndef _LPC32XX_CONFIG_H
#define _LPC32XX_CONFIG_H
/* Basic CPU architecture */
#if !defined(CFG_SYS_NS16550_CLK)

1
arch/arm/include/asm/arch-meson/gpio.h
View file

@ -6,5 +6,4 @@
#ifndef __ASM_ARCH_MESON_GPIO_H
#define __ASM_ARCH_MESON_GPIO_H
#endif /* __ASM_ARCH_MESON_GPIO_H */

1
arch/arm/include/asm/arch-mx27/gpio.h
View file

@ -4,7 +4,6 @@
* Philippe Reynes <tremyfr@yahoo.fr>
*/
#ifndef __ASM_ARCH_MX27_GPIO_H
#define __ASM_ARCH_MX27_GPIO_H

1
arch/arm/include/asm/arch-mx27/imx-regs.h
View file

@ -236,7 +236,6 @@ struct fuse_bank0_regs {
#define SDCS1_SEL (1 << 1)
#define SDCS0_SEL (1 << 0)
/* important definition of some bits of WCR */
#define WCR_WDE 0x04

1
arch/arm/include/asm/arch-mx31/gpio.h
View file

@ -4,7 +4,6 @@
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*/
#ifndef __ASM_ARCH_MX31_GPIO_H
#define __ASM_ARCH_MX31_GPIO_H

2
arch/arm/include/asm/arch-mx31/imx-regs.h
View file

@ -585,7 +585,6 @@ struct esdc_regs {
#define GET_PLL_MFI(x) (((x) >> 10) & 0xf)
#define GET_PLL_MFN(x) (((x) >> 0) & 0x3ff)
#define WEIM_ESDCTL0 0xB8001000
#define WEIM_ESDCFG0 0xB8001004
#define WEIM_ESDCTL1 0xB8001008
@ -777,7 +776,6 @@ struct esdc_regs {
#define MUX_CTL_NFC_ALE 0xD6
#define MUX_CTL_NFC_CLE 0xD7
#define MUX_CTL_CAPTURE 0x150
#define MUX_CTL_COMPARE 0x151

1
arch/arm/include/asm/arch-mx5/gpio.h
View file

@ -4,7 +4,6 @@
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*/
#ifndef __ASM_ARCH_MX5_GPIO_H
#define __ASM_ARCH_MX5_GPIO_H

1
arch/arm/include/asm/arch-mx6/gpio.h
View file

@ -4,7 +4,6 @@
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*/
#ifndef __ASM_ARCH_MX6_GPIO_H
#define __ASM_ARCH_MX6_GPIO_H

1
arch/arm/include/asm/arch-mx6/imx-regs.h
View file

@ -385,7 +385,6 @@
((is_mx6ull()) ? \
MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#define SRC_SCR_CORE_1_RESET_OFFSET 14

4
arch/arm/include/asm/arch-mx7/crm_regs.h
View file

@ -229,7 +229,6 @@ struct mxc_ccm_anatop_reg {
#define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5)
#define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12)
#define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f
#define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B
#define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016
@ -1784,7 +1783,6 @@ struct mxc_ccm_anatop_reg {
#define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24
#define PMU_LOWPWR_CTRL_TOG_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK)
/* HW_ANADIG_TEMPSENSE0 Bit Fields */
#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu
#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0
@ -1998,7 +1996,6 @@ struct mxc_ccm_anatop_reg {
#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29
#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK)
#define CCM_GPR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i))
#define CCM_OBSERVE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i))
#define CCM_SCTRL(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i))
@ -2091,7 +2088,6 @@ struct mxc_ccm_anatop_reg {
#define CLK_ROOT_ALT6 0x06000000
#define CLK_ROOT_ALT7 0x07000000
#define DRAM_CLK_ROOT_POST_DIV_MASK 0x00000007
#define CLK_ROOT_POST_DIV_MASK 0x0000003f
#define CLK_ROOT_POST_DIV_SHIFT 0

2
arch/arm/include/asm/arch-mx7/imx-regs.h
View file

@ -71,7 +71,6 @@
#define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200)
#define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600)
/* Defines for Blocks connected via AIPS (SkyBlue) */
#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
#define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
@ -1162,7 +1161,6 @@ struct rdc_sema_regs {
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
extern void check_cpu_temperature(void);
extern void pcie_power_up(void);

2
arch/arm/include/asm/arch-mx7ulp/imx-regs.h
View file

@ -124,7 +124,6 @@
#define IOMUXC_PSMI_IMUX_ALT6 (0x6)
#define IOMUXC_PSMI_IMUX_ALT7 (0x7)
#define SIM_SOPT1_EN_SNVS_HARD_RST (1<<8)
#define SIM_SOPT1_PMIC_STBY_REQ (1<<2)
#define SIM_SOPT1_A7_SW_RESET (1<<0)
@ -240,7 +239,6 @@
#define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34)))
#define IOMUXC_DPCR_DDR_DQS3 ((IOMUXC_DDR_RBASE + (4 * 35)))
#define IOMUXC_DPCR_DDR_DQ0 ((IOMUXC_DDR_RBASE + (4 * 0)))
#define IOMUXC_DPCR_DDR_DQ1 ((IOMUXC_DDR_RBASE + (4 * 1)))
#define IOMUXC_DPCR_DDR_DQ2 ((IOMUXC_DDR_RBASE + (4 * 2)))

2
arch/arm/include/asm/arch-mx7ulp/iomux.h
View file

@ -69,7 +69,6 @@ typedef u64 iomux_cfg_t;
#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
MUX_PAD_CTRL(pad))
#define IOMUX_CONFIG_MPORTS 0x20
#define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \
MUX_MODE_SHIFT)
@ -87,7 +86,6 @@ typedef u64 iomux_cfg_t;
#define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE)
#define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE)
void mx7ulp_iomux_setup_pad(iomux_cfg_t pad);
void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
unsigned count);

3
arch/arm/include/asm/arch-mx7ulp/pcc.h
View file

@ -278,7 +278,6 @@ enum pcc3_entry {
RSVD127_PCC3_SLOT = 127,
};
/* PCC registers */
#define PCC_PR_OFFSET 31
#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET)
@ -293,7 +292,6 @@ enum pcc3_entry {
#define PCC_PCD_OFFSET 0
#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET)
enum pcc_clksrc_type {
CLKSRC_PER_PLAT = 0,
CLKSRC_PER_BUS = 1,
@ -353,7 +351,6 @@ enum pcc_clk {
PER_CLK_GPU2D,
};
/* This structure keeps info for each pcc slot */
struct pcc_entry {
u32 pcc_base;

1
arch/arm/include/asm/arch-mx7ulp/scg.h
View file

@ -145,7 +145,6 @@
#define SCG_UPLL_CSR_UPLLVLD_MASK (0x01000000)
#define SCG_PLL_PFD3_GATE_MASK (0x80000000)
#define SCG_PLL_PFD2_GATE_MASK (0x00800000)
#define SCG_PLL_PFD1_GATE_MASK (0x00008000)

1
arch/arm/include/asm/arch-omap3/mem.h
View file

@ -463,7 +463,6 @@ enum {
#define NET_LAN9221_GPMC_CONFIG6 0x87030000
#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
/* max number of GPMC Chip Selects */
#define GPMC_MAX_CS 8
/* max number of GPMC regs */

1
arch/arm/include/asm/arch-omap3/mmc_host_def.h
View file

@ -63,5 +63,4 @@ typedef struct t2 {
#define OMAP_HSMMC2_BASE 0x480B4000
#define OMAP_HSMMC3_BASE 0x480AD000
#endif /* MMC_HOST_DEF_H */

1
arch/arm/include/asm/arch-omap4/clock.h
View file

@ -100,7 +100,6 @@
#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
/* CM_<clock_domain>_<module>_CLKCTRL */
#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
#define MODULE_CLKCTRL_MODULEMODE_MASK 3

1
arch/arm/include/asm/arch-omap5/clock.h
View file

@ -111,7 +111,6 @@
#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
/* CM_<clock_domain>_<module>_CLKCTRL */
#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
#define MODULE_CLKCTRL_MODULEMODE_MASK 3

1
arch/arm/include/asm/arch-omap5/gpio.h
View file

@ -33,7 +33,6 @@
#define OMAP54XX_GPIO7_BASE 0x48051000
#define OMAP54XX_GPIO8_BASE 0x48053000
/* Get the GPIO index from the given bank number and bank gpio */
#define GPIO_TO_PIN(bank, bank_gpio) (32 * (bank - 1) + (bank_gpio))

1
arch/arm/include/asm/arch-rockchip/edp_rk3288.h
View file

@ -532,7 +532,6 @@ check_member(rk3288_edp, pll_reg_5, 0xa00);
#define EDID_HEADER 0x00
#define EDID_EXTENSION_FLAG 0x7e
enum dpcd_request {
DPCD_READ,
DPCD_WRITE,

1
arch/arm/include/asm/arch-rockchip/lvds_rk3288.h
View file

@ -96,5 +96,4 @@
#define LVDS_24BIT (0 << 1)
#define LVDS_18BIT (1 << 1)
#endif

2
arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
View file

@ -262,7 +262,6 @@ struct sunxi_ccm_reg {
#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
#define CCM_DRAM_GATE_OFFSET_DE_BE1 27
#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6 / 2 */
#define MBUS_CLK_GATE (0x1 << 31)
@ -295,7 +294,6 @@ struct sunxi_ccm_reg {
#define APB2_RESET_TWI_SHIFT (0)
#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT)
#ifndef __ASSEMBLY__
void clock_set_pll1(unsigned int hz);
void clock_set_pll5(unsigned int clk);

1
arch/arm/include/asm/arch-sunxi/clock_sun9i.h
View file

@ -217,7 +217,6 @@ struct sunxi_ccm_reg {
#define APB1_RESET_TWI_SHIFT 0
#define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT)
#ifndef __ASSEMBLY__
void clock_set_pll1(unsigned int clk);
void clock_set_pll6(unsigned int clk);

1
arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
View file

@ -323,7 +323,6 @@ struct dram_para {
const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
};
static inline int ns_to_t(int nanoseconds)
{
const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;

1
arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
View file

@ -146,7 +146,6 @@ struct sunxi_mctl_ctl_reg {
u32 perfwr1; /* 0x1d8 */
};
#define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x)
#define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x)
#define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x)

2
arch/arm/include/asm/arch-sunxi/dram_sun9i.h
View file

@ -40,7 +40,6 @@ struct sunxi_mctl_com_reg {
u32 mdfstcr; /* 0x14c */
};
struct sunxi_mctl_ctl_reg {
u32 mstr; /* 0x00 master register */
u32 stat; /* 0x04 operating mode status register */
@ -92,7 +91,6 @@ struct sunxi_mctl_ctl_reg {
u32 perfwr1; /* 0x26c write CAM register 1 */
};
struct sunxi_mctl_phy_reg {
u8 res0[0x04]; /* 0x00 revision id ??? */
u32 pir; /* 0x04 PHY initialisation register */

3
arch/arm/include/asm/arch-tegra/bpmp_abi.h
View file

@ -29,7 +29,6 @@
* @file
*/
/**
* @defgroup MRQ MRQ Messages
* @brief Messages sent to/from BPMP via IPC
@ -167,7 +166,6 @@ struct mrq_response {
* @}
*/
/**
* @ingroup MRQ_Codes
* @def MRQ_PING
@ -616,7 +614,6 @@ struct mrq_debugfs_response {
#define DEBUGFS_S_IWUSR (1 << 7)
/** @} */
/**
* @ingroup MRQ_Codes
* @def MRQ_RESET

1
arch/arm/include/asm/arch-tegra/clock.h
View file

@ -130,7 +130,6 @@ void reset_periph(enum periph_id periph_id, int us_delay);
*/
void reset_set_enable(enum periph_id periph_id, int enable);
/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
enum crc_reset_id {
/* Things we can hold in reset for each CPU */

1
arch/arm/include/asm/arch-tegra/warmboot.h
View file

@ -117,7 +117,6 @@ union scratch3_reg {
u32 word;
};
/**
* Save warmboot memory settings for a later resume
*

1
arch/arm/include/asm/byteorder.h
View file

@ -15,7 +15,6 @@
#ifndef __ASM_ARM_BYTEORDER_H
#define __ASM_ARM_BYTEORDER_H
#include <asm/types.h>
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)

3
arch/arm/include/asm/emif.h
View file

@ -880,7 +880,6 @@ struct dmm_lisa_map_regs {
#define RL_FINAL 6
#endif
/* Interleaving policies at EMIF level- between banks and Chip Selects */
#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0
#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3
@ -913,7 +912,6 @@ struct dmm_lisa_map_regs {
*/
#define READ_IDLE_INTERVAL_NORMAL (50*1000)
/*
* Unless voltage is changing due to DVFS one ZQCS command every 50ms should
* be enough. This shoule be enough also in the case when voltage is changing
@ -961,7 +959,6 @@ struct dmm_lisa_map_regs {
#define REG_SR_TIM 0xF
#define REG_PD_TIM 0xF
/* EMIF_PWR_MGMT_CTRL register */
#define EMIF_PWR_MGMT_CTRL (\
((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\

1
arch/arm/include/asm/mach-imx/gpio.h
View file

@ -4,7 +4,6 @@
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*/
#ifndef __ASM_ARCH_IMX_GPIO_H
#define __ASM_ARCH_IMX_GPIO_H

1
arch/arm/include/asm/mach-imx/mxc_i2c.h
View file

@ -91,7 +91,6 @@ struct mxc_i2c_bus {
} \
};
#define I2C_PADS_INFO(name) \
(is_mx6dq() || is_mx6dqp()) ? &mx6q_##name : &mx6s_##name
#endif

1
arch/arm/include/asm/omap_common.h
View file

@ -814,7 +814,6 @@ static inline u8 is_dra76x_acd(void)
#define HS_DEVICE 0x2
#define GP_DEVICE 0x3
/*
* SRAM scratch space entries
*/

3
arch/arm/include/asm/opcodes.h
View file

@ -15,7 +15,6 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
#define ARM_OPCODE_CONDTEST_PASS 1
#define ARM_OPCODE_CONDTEST_UNCOND 2
/*
* Assembler opcode byteswap helpers.
* These are only intended for use by this header: don't use them directly,
@ -42,7 +41,6 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
/*
* Opcode byteswap helpers
*
@ -94,7 +92,6 @@ extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
#endif /* ! __ASSEMBLY__ */
#ifdef CONFIG_CPU_ENDIAN_BE8
#define __opcode_to_mem_arm(x) ___opcode_swab32(x)

1
arch/arm/include/asm/setup.h
View file

@ -75,7 +75,6 @@ struct param_struct {
char commandline[COMMAND_LINE_SIZE];
};
/*
* The new way of passing information: a list of tagged entries
*/

1
arch/arm/mach-at91/include/mach/at91_pio.h
View file

@ -13,7 +13,6 @@
#ifndef AT91_PIO_H
#define AT91_PIO_H
#define AT91_ASM_PIO_RANGE 0x200
#define AT91_ASM_PIOC_ASR \
(ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70)

1
arch/arm/mach-at91/include/mach/atmel_mpddrc.h
View file

@ -59,7 +59,6 @@ struct atmel_mpddr {
u32 version; /* 0xfc: IP version */
};
int ddr2_init(const unsigned int base,
const unsigned int ram_address,
const struct atmel_mpddrc_config *mpddr_value);

1
arch/arm/mach-at91/mpddrc.c
View file

@ -35,7 +35,6 @@ static int ddr2_decodtype_is_seq(const unsigned int base, u32 cr)
return 1;
}
int ddr2_init(const unsigned int base,
const unsigned int ram_address,
const struct atmel_mpddrc_config *mpddr_value)

1
arch/arm/mach-davinci/da850_lowlevel.c
View file

@ -146,7 +146,6 @@ static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
*/
setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
/*
* clear EMIFA and EMIFB clock source settings, let them
* run off SYSCLK

1
arch/arm/mach-exynos/common_setup.h
View file

@ -61,7 +61,6 @@ enum l2_cache_params {
CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
};
#if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
/*
* Configure L2CTLR to get timings that keep us from hanging/crashing.

2
arch/arm/mach-exynos/exynos4_setup.h
View file

@ -284,7 +284,6 @@
#define MFC_0_SEL MFC_SEL_MPLL
#define CLK_SRC_MFC_VAL ((MFC_SEL << 8) | (MFC_0_SEL))
/* CLK_DIV_MFC */
#define MFC_RATIO 3
#define CLK_DIV_MFC_VAL (MFC_RATIO)
@ -498,7 +497,6 @@ struct mem_timings {
| ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
| NUM_CHIP_2 | BL_8)
#define CHIP_BANK_8 (0x3 << 0)
#define CHIP_ROW_14 (0x2 << 4)
#define CHIP_COL_10 (0x3 << 8)

4
arch/arm/mach-exynos/exynos5_setup.h
View file

@ -685,7 +685,6 @@
#define PWM_RATIO 8
#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
/* CLK_DIV_PERIC4 */
#define CLK_DIV_PERIC4_VAL NOT_AVAILABLE
@ -710,7 +709,6 @@
/* MPLL_CON1 */
#define MPLL_CON1_VAL (0x0020F300)
/* CPLL_CON1 */
#define CPLL_CON1_VAL 0x0020f300
@ -720,7 +718,6 @@
/* GPLL_CON1 */
#define GPLL_CON1_VAL (NOT_AVAILABLE)
/* EPLL_CON1, CON2 */
#define EPLL_CON1_VAL 0x00000000
#define EPLL_CON2_VAL 0x00000080
@ -750,7 +747,6 @@
#define CLK_DIV_ISP0_VAL 0x13131300
#define CLK_DIV_ISP1_VAL 0xbb110202
/* CLK_FSYS */
#define CLK_SRC_FSYS0_VAL 0x33033300
#define CLK_DIV_FSYS0_VAL 0x0

1
arch/arm/mach-exynos/include/mach/cpu.h
View file

@ -190,7 +190,6 @@
#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
#ifndef __ASSEMBLY__
#include <asm/io.h>
/* CPU detection macros */

1
arch/arm/mach-exynos/include/mach/dp_info.h
View file

@ -183,7 +183,6 @@ enum {
VIDEO_TIMING_FROM_REGISTER
};
struct exynos_dp_platform_data {
struct exynos_dp_priv *edp_dev_info;
};

1
arch/arm/mach-exynos/include/mach/power.h
View file

@ -1752,7 +1752,6 @@ void set_xclkout(void);
*/
uint32_t get_reset_status(void);
/* Read the resume function and call it */
void power_exit_wakeup(void);

1
arch/arm/mach-exynos/include/mach/sound.h
View file

@ -4,7 +4,6 @@
* Rajeshwari Shinde <rajeshwari.s@samsung.com>
*/
#ifndef __SOUND_ARCH_H__
#define __SOUND_ARCH_H__

1
arch/arm/mach-exynos/pinmux.c
View file

@ -391,7 +391,6 @@ static void exynos5420_i2s_config(int peripheral)
}
}
void exynos5_spi_config(int peripheral)
{
int cfg = 0, pin = 0, i;

2
arch/arm/mach-exynos/power.c
View file

@ -20,7 +20,6 @@ static void exynos4_mipi_phy_control(unsigned int dev_index,
else
addr = (unsigned int)&pmu->mipi_phy1_control;
cfg = readl(addr);
if (enable)
cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
@ -174,7 +173,6 @@ void set_ps_hold_ctrl(void)
exynos5_set_ps_hold_ctrl();
}
static void exynos5_set_xclkout(void)
{
struct exynos5_power *power =

1
arch/arm/mach-imx/cache.c
View file

@ -86,7 +86,6 @@ void v7_outer_cache_enable(void)
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
unsigned int val, cache_id;
/*
* Must disable the L2 before changing the latency parameters
* and auxiliary control register.

2
arch/arm/mach-imx/imx8/cpu.c
View file

@ -519,7 +519,6 @@ phys_size_t get_effective_memsize(void)
board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
&phys_sdram_2_start, &phys_sdram_2_size);
end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
for (mr = 0; mr < 64; mr++) {
err = get_owned_memreg(mr, &start, &end);
@ -699,7 +698,6 @@ static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
&phys_sdram_2_start, &phys_sdram_2_size);
end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;

1
arch/arm/mach-imx/imx8m/clock_imx8mq.c
View file

@ -733,7 +733,6 @@ static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
return 0;
}
int clock_init(void)
{
u32 grade;

1
arch/arm/mach-imx/mx6/litesom.c
View file

@ -83,7 +83,6 @@ int litesom_mmc_init(struct bd_info *bis)
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000,

2
arch/arm/mach-imx/mx7ulp/scg.c
View file

@ -428,7 +428,6 @@ static u32 scg_nic_get_rate(enum scg_clk clk)
return rate;
}
static enum scg_clk scg_scs_array[4] = {
SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK,
};
@ -807,7 +806,6 @@ int scg_enable_usb_pll(bool usb_control)
return 0;
}
/* A7 domain system clock source is SPLL */
#define SCG1_RCCR_SCS_NUM ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT)

1
arch/arm/mach-keystone/include/mach/psc_defs.h
View file

@ -26,7 +26,6 @@
#define PSC_REG_MDSTAT(x) (0x800 + (4 * (x)))
#define PSC_REG_MDCTL(x) (0xa00 + (4 * (x)))
static inline u32 _boot_bit_mask(u32 x, u32 y)
{
u32 val = (1 << (x - y + 1)) - 1;

1
arch/arm/mach-keystone/msmc.c
View file

@ -53,7 +53,6 @@ struct msms_regs {
struct mpax ses[16][8];
};
void msmc_share_all_segments(int priv_id)
{
struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;

1
arch/arm/mach-kirkwood/mpp.c
View file

@ -48,7 +48,6 @@ void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save)
}
debug("\n");
while (*mpp_list) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);

1
arch/arm/mach-mvebu/mbus.c
View file

@ -276,7 +276,6 @@ static int mvebu_mbus_alloc_window(phys_addr_t base, size_t size,
target, attr);
}
for (win = 0; win < MVEBU_MBUS_NUM_WINS; win++)
if (mvebu_mbus_window_is_free(win))
return mvebu_mbus_setup_window(win, base, size,

5
arch/arm/mach-mvebu/serdes/axp/board_env_spec.h
View file

@ -76,7 +76,6 @@
#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24))
#define CORE_AVS_CONTROL_0REG 0x18300
#define CORE_AVS_CONTROL_2REG 0x18308
#define CPU_AVS_CONTROL2_REG 0x20868
@ -86,7 +85,6 @@
#define MSAR_TCLK_OFFS 28
#define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS)
/* Controler environment registers offsets */
#define GEN_PURP_RES_1_REG 0x182F4
#define GEN_PURP_RES_2_REG 0x182F8
@ -146,7 +144,6 @@
0x40000 + ((port) % 2) * 0x4000)
#define MV_ETH_REGS_BASE(port) MV_ETH_REGS_OFFSET(port)
#define SGMII_PWR_PLL_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xE04)
#define SGMII_DIG_LP_ENA_REG(port) (MV_ETH_REGS_BASE(port) + 0xE8C)
#define SGMII_REF_CLK_SEL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF18)
@ -182,7 +179,6 @@
#define SCR_PEX1_4BY1_OFFS 8
#define SCR_PEX1_4BY1_MASK (1 << SCR_PEX1_4BY1_OFFS)
#define MV_MISC_REGS_OFFSET (0x18200)
#define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET)
#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
@ -226,7 +222,6 @@
#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS)
#define PEX_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x60)
#define PEX_LINK_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x6C)
#define PEX_LINK_CTRL_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x70)

2
arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h
View file

@ -21,7 +21,6 @@ typedef enum {
SERDES_LAST_UNIT
} MV_BIN_SERDES_UNIT_INDX;
typedef enum {
PEX_BUS_DISABLED = 0,
PEX_BUS_MODE_X1 = 1,
@ -63,7 +62,6 @@ typedef struct board_serdes_conf {
MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
} MV_BIN_SERDES_CFG;
#define BIN_SERDES_CFG { \
{0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
{0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \

1
arch/arm/mach-omap2/am33xx/chilisom.c
View file

@ -102,7 +102,6 @@ void chilisom_spl_board_init(void)
/* Get the frequency */
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
if (i2c_probe(TPS65217_CHIP_PM))
return;

1
arch/arm/mach-omap2/am33xx/clock.c
View file

@ -213,7 +213,6 @@ void do_disable_clocks(u32 *const *clk_domains,
{
u32 i, max = 100;
/* Clock modules that need to be put in SW_DISABLE */
for (i = 0; (i < max) && clk_modules_disable && clk_modules_disable[i];
i++)

1
arch/arm/mach-omap2/am33xx/sys_info.c
View file

@ -74,7 +74,6 @@ u32 get_sys_clk_index(void)
CTRL_SYSBOOT_15_14_SHIFT);
}
#ifdef CONFIG_DISPLAY_CPUINFO
static char *cpu_revs[] = {
"1.0",

1
arch/arm/mach-omap2/clocks-common.c
View file

@ -896,7 +896,6 @@ void do_disable_clocks(u32 const *clk_domains,
{
u32 i, max = 100;
/* Clock modules that need to be put in SW_DISABLE */
for (i = 0; (i < max) && clk_modules_disable[i]; i++)
disable_clock_module(clk_modules_disable[i],

2
arch/arm/mach-omap2/hwinit-common.c
View file

@ -268,7 +268,6 @@ void watchdog_init(void)
writel(WD_UNLOCK2, &wd2_base->wspr);
}
/*
* This function finds the SDRAM size available in the system
* based on DMM section configurations
@ -315,7 +314,6 @@ u32 omap_sdram_size(void)
return total_size;
}
/*
* Routine: dram_init
* Description: sets uboots idea of sdram size

1
arch/arm/mach-omap2/omap3/board.c
View file

@ -405,7 +405,6 @@ void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{

1
arch/arm/mach-renesas/include/mach/rcar-base.h
View file

@ -328,7 +328,6 @@
#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
#endif /* R8A7792 */
#define SYS_AXI_AVBDMSCR 0xFF802000
#define SYS_AXI_SYX2DMSCR 0xFF802004
#define SYS_AXI_AX2MDMSCR 0xFF802004

1
arch/arm/mach-s5pc1xx/include/mach/cpu.h
View file

@ -45,7 +45,6 @@
#define S5PC110_PHY_BASE 0xEC100000
#define S5PC110_USB_PHY_CONTROL 0xE010E80C
#ifndef __ASSEMBLY__
#include <asm/io.h>
/* CPU detection macros */

1
arch/arm/mach-socfpga/clock_manager_gen5.c
View file

@ -125,7 +125,6 @@ int cm_basic_init(const struct cm_config * const cfg)
readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
/*
* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
* with numerator and denominator.

1
arch/arm/mach-socfpga/freeze_controller.c
View file

@ -3,7 +3,6 @@
* Copyright (C) 2013 Altera Corporation <www.altera.com>
*/
#include <config.h>
#include <asm/io.h>
#include <asm/arch/clock_manager.h>

1
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
View file

@ -106,7 +106,6 @@ void cm_basic_init(const struct cm_config * const cfg);
#define CLKMGR_INTER CLKMGR_S10_INTER
#define CLKMGR_PERPLL_EN CLKMGR_S10_PERPLL_EN
#define CLKMGR_CTRL_SAFEMODE BIT(0)
#define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007
#define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f

1
arch/arm/mach-socfpga/misc_soc64.c
View file

@ -39,7 +39,6 @@ static Altera_desc altera_fpga[] = {
},
};
/*
* Print CPU information
*/

1
arch/arm/mach-socfpga/reset_manager_gen5.c
View file

@ -3,7 +3,6 @@
* Copyright (C) 2013 Altera Corporation <www.altera.com>
*/
#include <mach/base_addr_ac5.h>
#include <asm/io.h>
#include <asm/arch/fpga_manager.h>

1
arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c
View file

@ -187,7 +187,6 @@ U_BOOT_CMD(stm32prog, 5, 0, do_stm32prog,
" <size> = size of flashlayout (optional for image with STM32 header)\n"
);
bool stm32prog_get_fsbl_nor(void)
{
if (stm32prog_data)

1
arch/arm/mach-sunxi/clock_sun8i_a83t.c
View file

@ -118,7 +118,6 @@ void clock_set_pll5(unsigned int clk)
udelay(5500);
}
unsigned int clock_get_pll6(void)
{
struct sunxi_ccm_reg *const ccm =

2
arch/arm/mach-sunxi/clock_sun9i.c
View file

@ -14,7 +14,6 @@
#include <asm/arch/prcm.h>
#include <asm/arch/sys_proto.h>
#ifdef CONFIG_SPL_BUILD
static void clock_set_pll2(unsigned int clk)
@ -166,7 +165,6 @@ void clock_set_pll6(unsigned int clk)
sdelay(2000);
}
int clock_twi_onoff(int port, int state)
{
struct sunxi_ccm_reg *const ccm =

1
arch/arm/mach-sunxi/dram_sun8i_a83t.c
View file

@ -284,7 +284,6 @@ static int mctl_channel_init(struct dram_para *para)
writel(0x0, MCTL_PROTECT);
udelay(100);
/* Set ODT */
if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
rval = 0x0;

1
arch/arm/mach-sunxi/dram_sun9i.c
View file

@ -262,7 +262,6 @@ static void mctl_sys_init(void)
reg_val |= ((0x1<<24)|(0x1<<30));
mctl_write_w(CCM_PLL6_DDR_REG, reg_val);
while(mctl_read_w(CCM_PLL6_DDR_REG) & (0x1<<30));
}

1
arch/arm/mach-sunxi/dram_sunxi_dw.c
View file

@ -650,7 +650,6 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
return 0;
}
static void mctl_auto_detect_dram_size_rank(uint16_t socid, struct dram_para *para, ulong base, struct rank_para *rank)
{
/* detect row address bits */

1
arch/m68k/include/asm/bitops.h
View file

@ -19,7 +19,6 @@ extern int test_and_change_bit(int nr, volatile void *addr);
#ifdef __KERNEL__
static inline int test_bit(int nr, __const__ volatile void *addr)
{
__const__ unsigned int *p = (__const__ unsigned int *) addr;

1
arch/m68k/include/asm/cache.h
View file

@ -136,7 +136,6 @@
#define CF_ACR_SP (1 << 3)
#endif /* CONFIG_CF_V4 */
#ifndef CFG_SYS_CACHE_ICACR
#define CFG_SYS_CACHE_ICACR 0
#endif

1
arch/m68k/include/asm/immap_5271.h
View file

@ -54,5 +54,4 @@
#include <asm/coldfire/rng.h>
#include <asm/coldfire/skha.h>
#endif /* __IMMAP_5271__ */

1
arch/m68k/include/asm/immap_5275.h
View file

@ -223,7 +223,6 @@ typedef struct gpio_ctrl {
u8 par_res2[3];
} gpio_t;
/* Watchdog registers
*/
typedef struct wdog_ctrl {

1
arch/m68k/include/asm/m5441x.h
View file

@ -700,7 +700,6 @@
#define GPIO_PAR_FEC_FEC_MII (0x01) /* MDC & MDIO - GPIO */
#define GPIO_PAR_FEC_FEC_MIIFUL (0x00)
/* TC: Need to edit here.... */
/* Mode Select Control */

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