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https://github.com/u-boot/u-boot.git
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xtensa: Remove duplicate newlines
Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
Tom Rini
parent
62b668ba13
commit
3451b69e33
12 changed files with 0 additions and 74 deletions
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@ -9,7 +9,6 @@
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#ifndef _XTENSA_CORE_CONFIGURATION_H
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#define _XTENSA_CORE_CONFIGURATION_H
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/****************************************************************************
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Parameters Useful for Any Code, USER or PRIVILEGED
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****************************************************************************/
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@ -19,7 +18,6 @@
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* configured, and a value of 0 otherwise. These macros are always defined.
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*/
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/*----------------------------------------------------------------------
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ISA
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----------------------------------------------------------------------*/
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@ -69,7 +67,6 @@
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#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
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#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
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/*----------------------------------------------------------------------
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MISC
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----------------------------------------------------------------------*/
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@ -111,7 +108,6 @@
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#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
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#define XCHAL_HW_MAX_VERSION 221001 /* latest targeted hw */
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/*----------------------------------------------------------------------
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CACHE
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----------------------------------------------------------------------*/
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@ -126,12 +122,10 @@
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#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
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/****************************************************************************
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Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
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****************************************************************************/
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#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
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/*----------------------------------------------------------------------
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@ -159,7 +153,6 @@
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/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
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#define XCHAL_CA_BITS 4
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/*----------------------------------------------------------------------
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INTERNAL I/D RAM/ROMs and XLMI
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----------------------------------------------------------------------*/
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@ -171,7 +164,6 @@
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#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
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#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
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/*----------------------------------------------------------------------
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INTERRUPTS and TIMERS
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----------------------------------------------------------------------*/
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@ -282,7 +274,6 @@
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#define XCHAL_INTLEVEL7_NUM 14
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/* (There are many interrupts each at level(s) 1, 3.) */
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/*
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* External interrupt vectors/levels.
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* These macros describe how Xtensa processor interrupt numbers
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@ -311,7 +302,6 @@
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#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
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#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
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/*----------------------------------------------------------------------
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EXCEPTIONS and VECTORS
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----------------------------------------------------------------------*/
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@ -379,7 +369,6 @@
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#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
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#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
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/*----------------------------------------------------------------------
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DEBUG
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----------------------------------------------------------------------*/
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@ -389,7 +378,6 @@
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#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
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#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
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/*----------------------------------------------------------------------
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MMU
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----------------------------------------------------------------------*/
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@ -415,5 +403,4 @@
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#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
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#endif /* _XTENSA_CORE_CONFIGURATION_H */
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@ -25,7 +25,6 @@
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/* Misc */
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#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
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/* Macro to save all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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* Save area ptr (clobbered): ptr (1 byte aligned)
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@ -9,7 +9,6 @@
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#ifndef _XTENSA_CORE_CONFIGURATION_H
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#define _XTENSA_CORE_CONFIGURATION_H
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/****************************************************************************
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Parameters Useful for Any Code, USER or PRIVILEGED
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****************************************************************************/
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@ -19,7 +18,6 @@
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* configured, and a value of 0 otherwise. These macros are always defined.
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*/
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/*----------------------------------------------------------------------
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ISA
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----------------------------------------------------------------------*/
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@ -86,7 +84,6 @@
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#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
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#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
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/*----------------------------------------------------------------------
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MISC
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----------------------------------------------------------------------*/
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@ -130,7 +127,6 @@
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#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
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#define XCHAL_HW_MAX_VERSION 240001 /* latest targeted hw */
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/*----------------------------------------------------------------------
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CACHE
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----------------------------------------------------------------------*/
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@ -148,7 +144,6 @@
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#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
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/****************************************************************************
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Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
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****************************************************************************/
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@ -184,7 +179,6 @@
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/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
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#define XCHAL_CA_BITS 4
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/*----------------------------------------------------------------------
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INTERNAL I/D RAM/ROMs and XLMI
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----------------------------------------------------------------------*/
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@ -198,7 +192,6 @@
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#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
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/*----------------------------------------------------------------------
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INTERRUPTS and TIMERS
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----------------------------------------------------------------------*/
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@ -309,7 +302,6 @@
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#define XCHAL_INTLEVEL7_NUM 14
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/* (There are many interrupts each at level(s) 1, 3.) */
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/*
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* External interrupt vectors/levels.
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* These macros describe how Xtensa processor interrupt numbers
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@ -338,7 +330,6 @@
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#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
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#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
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/*----------------------------------------------------------------------
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EXCEPTIONS and VECTORS
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----------------------------------------------------------------------*/
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@ -408,7 +399,6 @@
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#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
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#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
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/*----------------------------------------------------------------------
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DEBUG
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----------------------------------------------------------------------*/
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@ -418,7 +408,6 @@
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#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
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#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
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/*----------------------------------------------------------------------
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MMU
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----------------------------------------------------------------------*/
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@ -445,5 +434,4 @@
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#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
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#endif /* _XTENSA_CORE_CONFIGURATION_H */
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@ -159,7 +159,6 @@
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.endif
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.endm // xchal_ncp_load
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#define XCHAL_NCP_NUM_ATMPS 1
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#define XCHAL_SA_NUM_ATMPS 1
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@ -9,7 +9,6 @@
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#ifndef _XTENSA_CORE_CONFIGURATION_H
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#define _XTENSA_CORE_CONFIGURATION_H
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/****************************************************************************
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Parameters Useful for Any Code, USER or PRIVILEGED
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****************************************************************************/
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@ -19,7 +18,6 @@
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* configured, and a value of 0 otherwise. These macros are always defined.
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*/
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/*----------------------------------------------------------------------
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ISA
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----------------------------------------------------------------------*/
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@ -91,7 +89,6 @@
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#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
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#define XCHAL_HAVE_HIFI_MINI 0
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#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
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#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
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#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
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@ -130,7 +127,6 @@
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#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
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#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
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/*----------------------------------------------------------------------
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MISC
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----------------------------------------------------------------------*/
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@ -178,7 +174,6 @@
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#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
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#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
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/*----------------------------------------------------------------------
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CACHE
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----------------------------------------------------------------------*/
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@ -205,7 +200,6 @@
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#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
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#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
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/****************************************************************************
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Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
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****************************************************************************/
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@ -250,7 +244,6 @@
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XCHAL_HAVE_DCACHE_DYN_WAYS) && \
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(XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
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/*----------------------------------------------------------------------
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INTERNAL I/D RAM/ROMs and XLMI
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----------------------------------------------------------------------*/
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@ -283,7 +276,6 @@
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#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
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/*----------------------------------------------------------------------
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INTERRUPTS and TIMERS
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----------------------------------------------------------------------*/
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@ -395,7 +387,6 @@
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#define XCHAL_INTLEVEL7_NUM 14
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/* (There are many interrupts each at level(s) 1, 3.) */
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/*
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* External interrupt mapping.
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* These macros describe how Xtensa processor interrupt numbers
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@ -442,7 +433,6 @@
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#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
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#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
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/*----------------------------------------------------------------------
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EXCEPTIONS and VECTORS
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----------------------------------------------------------------------*/
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@ -512,7 +502,6 @@
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#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
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#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
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/*----------------------------------------------------------------------
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DEBUG MODULE
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----------------------------------------------------------------------*/
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@ -539,7 +528,6 @@
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/* Perf counters */
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#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
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/*----------------------------------------------------------------------
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MMU
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----------------------------------------------------------------------*/
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@ -564,5 +552,4 @@
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#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
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#endif /* _XTENSA_CORE_CONFIGURATION_H */
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@ -31,7 +31,6 @@
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| ((ccuse) & XTHAL_SAS_ANYCC) \
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| ((abi) & XTHAL_SAS_ANYABI) )
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/*
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* Macro to store all non-coprocessor (extra) custom TIE and optional state
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* (not including zero-overhead loop registers).
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@ -140,7 +139,6 @@
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.endif
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.endm // xchal_ncp_load
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#define XCHAL_NCP_NUM_ATMPS 1
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#define XCHAL_SA_NUM_ATMPS 1
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@ -59,7 +59,6 @@
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loop \at, 99f
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.endm
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.macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
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.ifgt \incr_log2 - 1
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addi \at, \as, (1 << \incr_log2) - 1
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@ -72,7 +71,6 @@
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loop\cond \at, 99f
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.endm
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.macro __loopt ar, as, at, incr_log2
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sub \at, \as, \ar
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.ifgt \incr_log2 - 1
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@ -82,17 +80,14 @@
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loop \at, 99f
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.endm
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.macro __loop as
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loop \as, 99f
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.endm
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.macro __endl ar, as
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99:
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.endm
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#else
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.macro __loopi ar, at, size, incr
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@ -101,7 +96,6 @@
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98:
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.endm
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.macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
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.ifnc \mask_log2,
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extui \at, \as, \incr_log2, \mask_log2
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@ -127,25 +121,20 @@
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98:
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.endm
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.macro __loop as
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98:
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.endm
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.macro __endl ar, as
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bltu \ar, \as, 98b
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99:
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.endm
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#endif
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.macro __endla ar, as, incr
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addi \ar, \ar, \incr
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__endl \ar \as
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.endm
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#endif /* _XTENSA_ASMMACRO_H */
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@ -51,7 +51,6 @@
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.endm
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.macro __loop_cache_range ar as at insn line_width
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extui \at, \ar, 0, \line_width
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@ -63,7 +62,6 @@
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.endm
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.macro __loop_cache_page ar at insn line_width
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__loopi \ar, \at, PAGE_SIZE, 4 << (\line_width)
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@ -77,7 +75,6 @@
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.endm
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.macro ___unlock_dcache_all ar at
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#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
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@ -86,7 +83,6 @@
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.endm
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.macro ___unlock_icache_all ar at
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#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
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@ -95,7 +91,6 @@
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.endm
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.macro ___flush_invalidate_dcache_all ar at
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#if XCHAL_DCACHE_SIZE
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@ -104,7 +99,6 @@
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.endm
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.macro ___flush_dcache_all ar at
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#if XCHAL_DCACHE_SIZE
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@ -113,7 +107,6 @@
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.endm
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.macro ___invalidate_dcache_all ar at
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#if XCHAL_DCACHE_SIZE
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@ -123,7 +116,6 @@
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.endm
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.macro ___invalidate_icache_all ar at
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#if XCHAL_ICACHE_SIZE
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@ -133,7 +125,6 @@
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.endm
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.macro ___flush_invalidate_dcache_range ar as at
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#if XCHAL_DCACHE_SIZE
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@ -142,7 +133,6 @@
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.endm
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.macro ___flush_dcache_range ar as at
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#if XCHAL_DCACHE_SIZE
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@ -151,7 +141,6 @@
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.endm
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.macro ___invalidate_dcache_range ar as at
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#if XCHAL_DCACHE_SIZE
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@ -160,7 +149,6 @@
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.endm
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.macro ___invalidate_icache_range ar as at
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#if XCHAL_ICACHE_SIZE
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@ -169,7 +157,6 @@
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.endm
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.macro ___flush_invalidate_dcache_page ar as
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#if XCHAL_DCACHE_SIZE
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@ -178,7 +165,6 @@
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.endm
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.macro ___flush_dcache_page ar as
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#if XCHAL_DCACHE_SIZE
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@ -187,7 +173,6 @@
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.endm
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.macro ___invalidate_dcache_page ar as
|
||||
|
||||
#if XCHAL_DCACHE_SIZE
|
||||
|
|
@ -196,7 +181,6 @@
|
|||
|
||||
.endm
|
||||
|
||||
|
||||
.macro ___invalidate_icache_page ar as
|
||||
|
||||
#if XCHAL_ICACHE_SIZE
|
||||
|
|
|
|||
|
|
@ -111,7 +111,6 @@ void outsl(unsigned long port, const void *src, unsigned long count);
|
|||
# error processor byte order undefined!
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Convert a physical pointer to a virtual kernel pointer for /dev/mem access
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -6,5 +6,4 @@
|
|||
#ifndef _XTENSA_PROCESSOR_H
|
||||
#define _XTENSA_PROCESSOR_H
|
||||
|
||||
|
||||
#endif /* _XTENSA_PROCESSOR_H */
|
||||
|
|
|
|||
|
|
@ -24,7 +24,6 @@ typedef u32 dma_addr_t;
|
|||
typedef unsigned long phys_addr_t;
|
||||
typedef unsigned long phys_size_t;
|
||||
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* _XTENSA_TYPES_H */
|
||||
|
|
|
|||
|
|
@ -62,7 +62,6 @@ void __udelay(unsigned long usec)
|
|||
delay_cycles(mhz * lo);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Return the elapsed time (ticks) since 'base'.
|
||||
*/
|
||||
|
|
@ -89,7 +88,6 @@ ulong get_timer(ulong base)
|
|||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* This function is derived from ARM/PowerPC code (read timebase as long long).
|
||||
* On Xtensa it just returns the timer value.
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue