Djam/u-boot
1
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2025-04-16 09:54:35 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Prepare v2025.01-rc4

Browse source 
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmdXaqUACgkQFHw5/5Y0
 tyzwDQv/W1C47W86RQKdu6LmlaJEQU/LV1wS6AvhxHtWvrWwg85/yIuiIErRbMyk
 +4Nof/grgie2j8lVGMEkABDdLdRwW4J70/TZn/w3NLBVKCU8dYAfCfWPo6mJeJkr
 tYupNkxDCMGA4EUkSNc/wdjH2yubMD2+wEaBf2Hz2Yp0B8BKGJg9Vf09YWQQHof0
 rByq4ThZ41W9njwk03UdcacN3HzVml7iJfoEg8RmqHThomQKD2WMNeCthzQUgRI2
 /sk8jNNyUli+/wzNlFqjYUKPB+V2DWxjVDNnrxvcb2i+Whgrb7+3rPtP7zhR3WVc
 oaHmW8CVe5/fhykrDHKG+IeLc59C1YOF3O9jG5LpjEoWDvTnt9Tnr+Rg4TYcAUdI
 4RhA16RSHmKs5MVnxF9xD9iIZ8x9WSq2cqkTHUAVbes2gyS4ITvXmoP674Khao8C
 qmtEJpz51Ye7g2OmfKB2Nr4C7fOWNkgq0teLjxZ7rdwuPyMRtsurY7j5Sw96AxWY
 HkWm6svP
 =5zS1
 -----END PGP SIGNATURE-----

Merge tag 'v2025.01-rc4' into next

Prepare v2025.01-rc4
This commit is contained in:
Tom Rini 2024-12-09 16:29:47 -06:00
commit 9bc62c980d
143 changed files with 1166 additions and 3474 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
Makefile
View file

@ -3,7 +3,7 @@
VERSION = 2025
PATCHLEVEL = 01
SUBLEVEL =
EXTRAVERSION = -rc3
EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*
@ -21,7 +21,7 @@ include include/host_arch.h
ifeq ("", "$(CROSS_COMPILE)")
MK_ARCH="${shell uname -m}"
else
MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(ccache\)\?[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}"
MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}"
endif
unexport HOST_ARCH
ifeq ("x86_64", $(MK_ARCH))

3
arch/arm/dts/Makefile
View file

@ -190,7 +190,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
cn9130-crb-A.dtb \
cn9130-crb-B.dtb \
ac5-98dx35xx-rd.dtb \
ac5-98dx35xx-atl-x240.dtb
ac5-98dx35xx-atl-x240.dtb \
cn9130-atl-x250.dtb
endif
dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb

126
arch/arm/dts/bcm47622.dtsi
View file

@ -1,126 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm47622", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>,
<&CA7_2>, <&CA7_3>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
cpu_off = <1>;
cpu_on = <2>;
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x818000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x2000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

128
arch/arm/dts/bcm4912.dtsi
View file

@ -1,128 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm4912", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_2: cpu@2 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_3: cpu@3 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>,
<&B53_2>, <&B53_3>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

110
arch/arm/dts/bcm63146.dtsi
View file

@ -1,110 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm63146", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

278
arch/arm/dts/bcm63158.dtsi
View file

@ -1,278 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm63158", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_2: cpu@2 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_3: cpu@3 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>,
<&B53_2>, <&B53_3>;
};
clocks {
bootph-all;
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
wdt_clk: wdt-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
bootph-all;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
leds: led-controller@800 {
compatible = "brcm,bcm6858-leds";
reg = <0x800 0xe4>;
status = "disabled";
};
wdt1: watchdog@480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x480 0x14>;
clocks = <&wdt_clk>;
};
wdt2: watchdog@4c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x4c0 0x14>;
clocks = <&wdt_clk>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt1>;
};
gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x4>,
<0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x4>,
<0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x4>,
<0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x4>,
<0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x4>,
<0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x4>,
<0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x4>,
<0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x4>,
<0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
hsspi: spi-controller@1000 {
compatible = "brcm,bcm6328-hsspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1000 0x600>;
clocks = <&hsspi_pll>, <&hsspi_pll>;
clock-names = "hsspi", "pll";
spi-max-frequency = <100000000>;
num-cs = <8>;
status = "disabled";
};
nand: nand-controller@1800 {
compatible = "brcm,nand-bcm63158",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x1800 0x180>,
<0x2000 0x10>,
<0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";
};
};
};

120
arch/arm/dts/bcm63178.dtsi
View file

@ -1,120 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm63178", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>,
<&CA7_2>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

130
arch/arm/dts/bcm6756.dtsi
View file

@ -1,130 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm6756", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>,
<&CA7_2>, <&CA7_3>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

128
arch/arm/dts/bcm6813.dtsi
View file

@ -1,128 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm6813", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_2: cpu@2 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_3: cpu@3 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>,
<&B53_2>, <&B53_3>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

257
arch/arm/dts/bcm6855.dtsi
View file

@ -1,257 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com>
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm6855", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
};
clocks: clocks {
bootph-all;
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
wdt_clk: wdt-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
bootph-all;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
wdt1: watchdog@480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x480 0x14>;
clocks = <&wdt_clk>;
};
wdt2: watchdog@4c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x4c0 0x14>;
clocks = <&wdt_clk>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt1>;
};
gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x4>,
<0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x4>,
<0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x4>,
<0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x4>,
<0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x4>,
<0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x4>,
<0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x4>,
<0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x4>,
<0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
nand: nand-controller@1800 {
compatible = "brcm,nand-bcm6753",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x1800 0x180>,
<0x2000 0x10>,
<0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";
};
leds: led-controller@3000 {
compatible = "brcm,bcm6753-leds";
reg = <0x3000 0x3480>;
status = "disabled";
};
};
};

253
arch/arm/dts/bcm6856.dtsi
View file

@ -1,253 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm6856", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>;
};
clocks: clocks {
bootph-all;
periph_clk:periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
wdt_clk: wdt-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>, /* GICD */
<0x2000 0x2000>, /* GICC */
<0x4000 0x2000>, /* GICH */
<0x6000 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
bootph-all;
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
reg = <0x640 0x18>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "refclk";
status = "disabled";
};
wdt1: watchdog@480 {
compatible = "brcm,bcm6345-wdt";
reg = <0x480 0x14>;
clocks = <&wdt_clk>;
};
wdt2: watchdog@4c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x4c0 0x14>;
clocks = <&wdt_clk>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt1>;
};
leds: led-controller@800 {
compatible = "brcm,bcm6858-leds";
reg = <0x800 0xe4>;
status = "disabled";
};
gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x4>,
<0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x4>,
<0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x4>,
<0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x4>,
<0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x4>,
<0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x4>,
<0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x4>,
<0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x4>,
<0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
hsspi: spi-controller@1000 {
compatible = "brcm,bcm6328-hsspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1000 0x600>;
clocks = <&hsspi_pll>, <&hsspi_pll>;
clock-names = "hsspi", "pll";
spi-max-frequency = <100000000>;
num-cs = <8>;
status = "disabled";
};
nand: nand-controller@1800 {
compatible = "brcm,nand-bcm68360",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x1800 0x180>,
<0x2000 0x10>,
<0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";
};
};
};

272
arch/arm/dts/bcm6858.dtsi
View file

@ -1,272 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "brcm,bcm6858", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
B53_0: cpu@0 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_1: cpu@1 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_2: cpu@2 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B53_3: cpu@3 {
compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B53_0>, <&B53_1>,
<&B53_2>, <&B53_3>;
};
clocks {
bootph-all;
periph_clk: periph_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
wdt_clk: wdt-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>, /* GICD */
<0x2000 0x2000>, /* GICC */
<0x4000 0x2000>, /* GICH */
<0x6000 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
bootph-all;
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
reg = <0x640 0x18>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "refclk";
status = "disabled";
};
leds: led-controller@800 {
compatible = "brcm,bcm6858-leds";
reg = <0x800 0xe4>;
status = "disabled";
};
wdt1: watchdog@2780 {
compatible = "brcm,bcm6345-wdt";
reg = <0x2780 0x14>;
clocks = <&wdt_clk>;
};
wdt2: watchdog@27c0 {
compatible = "brcm,bcm6345-wdt";
reg = <0x27c0 0x14>;
clocks = <&wdt_clk>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdt1>;
};
gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
reg = <0x500 0x4>,
<0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
reg = <0x504 0x4>,
<0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
reg = <0x508 0x4>,
<0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
reg = <0x50c 0x4>,
<0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
reg = <0x510 0x4>,
<0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
reg = <0x514 0x4>,
<0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
reg = <0x518 0x4>,
<0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
reg = <0x51c 0x4>,
<0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
hsspi: spi-controller@1000 {
compatible = "brcm,bcm6328-hsspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1000 0x600>;
clocks = <&hsspi_pll>, <&hsspi_pll>;
clock-names = "hsspi", "pll";
spi-max-frequency = <100000000>;
num-cs = <8>;
status = "disabled";
};
nand: nand-controller@1800 {
compatible = "brcm,nand-bcm6858",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
reg = <0x1800 0x180>,
<0x2000 0x10>,
<0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";
};
};
};

111
arch/arm/dts/bcm6878.dtsi
View file

@ -1,111 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm6878", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
CA7_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
CA7_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured;
};
pmu: pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&CA7_0>, <&CA7_1>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clocks = <&periph_clk>;
clock-div = <4>;
clock-mult = <1>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

30
arch/arm/dts/bcm947622.dts
View file

@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm47622.dtsi"
/ {
model = "Broadcom BCM947622 Reference Board";
compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm94912.dts
View file

@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm4912.dtsi"
/ {
model = "Broadcom BCM94912 Reference Board";
compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm963146.dts
View file

@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm63146.dtsi"
/ {
model = "Broadcom BCM963146 Reference Board";
compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm963158.dts
View file

@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm63158.dtsi"
/ {
model = "Broadcom BCM963158 Reference Board";
compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm963178.dts
View file

@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm63178.dtsi"
/ {
model = "Broadcom BCM963178 Reference Board";
compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm96756.dts
View file

@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6756.dtsi"
/ {
model = "Broadcom BCM96756 Reference Board";
compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm96813.dts
View file

@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6813.dtsi"
/ {
model = "Broadcom BCM96813 Reference Board";
compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm96855.dts
View file

@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6855.dtsi"
/ {
model = "Broadcom BCM96855 Reference Board";
compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm96856.dts
View file

@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6856.dtsi"
/ {
model = "Broadcom BCM96856 Reference Board";
compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm96858.dts
View file

@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6858.dtsi"
/ {
model = "Broadcom BCM96858 Reference Board";
compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

30
arch/arm/dts/bcm96878.dts
View file

@ -1,30 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm6878.dtsi"
/ {
model = "Broadcom BCM96878 Reference Board";
compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};

274
arch/arm/dts/cn9130-atl-x250.dts Normal file
View file

@ -0,0 +1,274 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024 Allied Telesis Labs
*/
#include "cn9130.dtsi"
/ {
model = "Allied Telesis x250";
compatible = "alliedtelesis,x250",
"marvell,cn9130",
"marvell,armada-ap806-quad",
"marvell,armada-ap806";
aliases {
serial0 = &uart0;
i2c0 = &cp0_i2c0;
i2c1 = &cp0_i2c1;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
fault {
label = "fault:red";
gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
default-state = "on";
};
};
};
/*
* AP related configuration
*/
&ap_pinctl {
/* AP_MPP Pins:
* GPIO & NC [0-6,9-10,12]
* UART0 [11,19]
* UART1 [7,8]
* Note: The x250-28XTm PT1 units has the console port wired
* to the second uart pins (UART1). This was fixed in all
* subsequent models.
* Here we choose to configure the pin control for both
* uarts to cater for either unit.
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 0 0 0 0 0 0 0 3 3 0
0 3 0 0 0 0 0 0 0 3 >;
};
&ap_gpio0 {
pp-reset {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
output-high;
line-name = "pp-reset";
};
};
/*
* CP related configuration
*/
&cp0_pinctl {
/* MPP Bus:
* [0-1] DEV
* [2-8] GPIO
* [9] DEV
* [10-12] GPIO
* [13] ND_RB
* [14] GPIO
* [15-28] DEV
* [29-30] GPIO
* [31] DEV
* [32-34] GPIO
* [35-36] I2C1
* [37-38] I2C0
* [39-55] GPIO
* [56-60] SPI
* [61-62] GPIO
*/
/* 0 1 2 3 4 5 6 7 8 9 */
pin-func = < 1 1 0 0 0 0 0 0 0 1
0 0 0 2 0 1 1 1 1 1
1 1 1 1 1 1 1 1 1 0
0 1 0 0 0 2 2 2 2 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 6 6 6 6
6 0 0>;
cp0_i2c0_pins: cp0-i2c-pins-0 {
marvell,pins = <37 38>;
marvell,function = <2>;
};
cp0_i2c0_gpio_pins: cp0-i2c-gpio-pins-0 {
marvell,pins = <37 38>;
marvell,function = <0>;
};
cp0_i2c1_pins: cp0-i2c-pins-1 {
marvell,pins = <35 36>;
marvell,function = <2>;
};
cp0_nand_pins: cp0-nand-pins {
marvell,pins = <0 1 9 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31>;
marvell,function = <1>;
};
cp0_nand_rb: cp0-nand-rb {
marvell,pins = <13>;
marvell,function = <2>;
};
cp0_spi0_pins: cp0-spi-pins-0 {
marvell,pins = <56 57 58 59 60>;
marvell,function = <6>;
};
};
&cp0_comphy {
phy0 {
phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
phy-type = <COMPHY_TYPE_IGNORE>;
};
phy2 {
phy-type = <COMPHY_TYPE_IGNORE>;
};
phy3 {
phy-type = <COMPHY_TYPE_IGNORE>;
};
phy4 {
phy-type = <COMPHY_TYPE_IGNORE>;
};
phy5 {
phy-type = <COMPHY_TYPE_IGNORE>;
};
};
&cp0_pcie0 {
num-lanes = <1>;
/* non-prefetchable memory */
ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
status = "disabled";
};
&uart0 {
status = "okay";
};
&uart1 {
clock-frequency = <200000000>;
};
&cp0_utmi0 {
status = "okay";
};
&cp0_usb3_0 {
status = "okay";
};
&cp0_spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi0_pins>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
};
};
&cp0_nand {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-timing-mode = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@user {
reg = <0x00000000 0x10000000>;
label = "user";
};
};
};
&cp0_gpio0
{
nand-protect {
gpio-hog;
gpios = <29 GPIO_ACTIVE_LOW>;
output-low;
line-name = "nand-protect";
};
};
&cp0_gpio1
{
usb-en {
gpio-hog;
gpios = <0 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-en";
};
phy-reset {
gpio-hog;
gpios = <21 GPIO_ACTIVE_LOW>;
output-high;
line-name = "phy-reset";
};
};
&cp0_i2c0 {
status = "okay";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&cp0_i2c0_pins>;
pinctrl-1 = <&cp0_i2c0_gpio_pins>;
scl-gpios = <&cp0_gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&cp0_gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
mux@71 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,pca9546";
reg = <0x71>;
i2c-mux-idle-disconnect;
reset-gpios = <&cp0_gpio1 19 GPIO_ACTIVE_LOW>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
hwmon@2e {
compatible = "adi,adt7476";
reg = <0x2e>;
};
rtc@68 {
compatible = "adi,max31331";
reg = <0x68>;
};
};
};
};
&cp0_i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c1_pins>;
};

11
arch/arm/dts/exynos850-e850-96-u-boot.dtsi
View file

@ -3,17 +3,6 @@
* Copyright (c) 2023 Linaro Ltd.
*/
&soc {
/* TODO: Remove this node once it appears in upstream dts */
trng: rng@12081400 {
compatible = "samsung,exynos850-trng";
reg = <0x12081400 0x100>;
clocks = <&cmu_core CLK_GOUT_SSS_ACLK>,
<&cmu_core CLK_GOUT_SSS_PCLK>;
clock-names = "secss", "pclk";
};
};
&pmu_system_controller {
bootph-all;
samsung,uart-debug-1;

25
arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi
View file

@ -16,6 +16,12 @@
dmo,ram-coding-gpios = <&gpio2 8 0>, <&gpio2 1 0>, <&gpio2 0 0>;
};
clk_pcie100: clk-pcie100 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
@ -35,6 +41,15 @@
bootph-pre-ram;
};
&pcie_phy {
clocks = <&clk_pcie100>;
};
&pcie0 {
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk_pcie100>;
};
&pinctrl_hog_sbc {
bootph-pre-ram;
};
@ -77,6 +92,7 @@
&gpio2 {
bootph-pre-ram;
bootph-some-ram;
dsi-reset-hog {
bootph-pre-ram;
@ -144,8 +160,17 @@
bootph-pre-ram;
};
&usbmisc1 {
bootph-pre-ram;
};
&usbphynop1 {
bootph-pre-ram;
};
&usbotg1 {
dr_mode = "peripheral";
bootph-pre-ram;
};
&usdhc2 {

2
arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
View file

@ -64,6 +64,7 @@
&gpio3 {
bootph-pre-ram;
bootph-some-ram;
bl-enable-hog {
bootph-pre-ram;
@ -92,6 +93,7 @@
&gpio4 {
bootph-pre-ram;
bootph-some-ram;
dsi-reset-hog {
bootph-pre-ram;

8
arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
View file

@ -13,6 +13,14 @@
};
};
&avb1 {
status = "disabled";
};
&avb2 {
status = "disabled";
};
&rpc {
flash@0 {
spi-tx-bus-width = <1>;

0
arch/arm/dts/socfpga_stratix10.dtsi Executable file → Normal file
View file

0
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi Executable file → Normal file
View file

0
arch/arm/dts/socfpga_stratix10_socdk.dts Executable file → Normal file
View file

1
arch/arm/mach-bcmbca/bcm47622/Kconfig
View file

@ -8,6 +8,7 @@ if BCM47622
config TARGET_BCM947622
bool "Broadcom 47622 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm47622"

1
arch/arm/mach-bcmbca/bcm4912/Kconfig
View file

@ -8,6 +8,7 @@ if BCM4912
config TARGET_BCM94912
bool "Broadcom 4912 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm4912"

1
arch/arm/mach-bcmbca/bcm63146/Kconfig
View file

@ -8,6 +8,7 @@ if BCM63146
config TARGET_BCM963146
bool "Broadcom 63146 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm63146"

1
arch/arm/mach-bcmbca/bcm63158/Kconfig
View file

@ -8,6 +8,7 @@ if BCM63158
config TARGET_BCM963158
bool "Broadcom 63158 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm63158"

1
arch/arm/mach-bcmbca/bcm63178/Kconfig
View file

@ -8,6 +8,7 @@ if BCM63178
config TARGET_BCM963178
bool "Broadcom 63178 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm63178"

1
arch/arm/mach-bcmbca/bcm6756/Kconfig
View file

@ -8,6 +8,7 @@ if BCM6756
config TARGET_BCM96756
bool "Broadcom 6756 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6756"

1
arch/arm/mach-bcmbca/bcm6813/Kconfig
View file

@ -8,6 +8,7 @@ if BCM6813
config TARGET_BCM96813
bool "Broadcom 6813 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6813"

1
arch/arm/mach-bcmbca/bcm6855/Kconfig
View file

@ -8,6 +8,7 @@ if BCM6855
config TARGET_BCM96855
bool "Broadcom 6855 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6855"

1
arch/arm/mach-bcmbca/bcm6856/Kconfig
View file

@ -8,6 +8,7 @@ if BCM6856
config TARGET_BCM96856
bool "Broadcom 6856 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6856"

1
arch/arm/mach-bcmbca/bcm6858/Kconfig
View file

@ -8,6 +8,7 @@ if BCM6858
config TARGET_BCM96858
bool "Broadcom 6858 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6858"

1
arch/arm/mach-bcmbca/bcm6878/Kconfig
View file

@ -8,6 +8,7 @@ if BCM6878
config TARGET_BCM96878
bool "Broadcom 6878 Reference Board"
depends on ARCH_BCMBCA
imply OF_UPSTREAM
config SYS_SOC
default "bcm6878"

10
arch/arm/mach-mvebu/Kconfig
View file

@ -215,9 +215,16 @@ config TARGET_X530
bool "Support Allied Telesis x530"
select 88F6820
config TARGET_X250
bool "Support Allied Telesis x250"
select ARMADA_8K
imply SCSI
imply BOOTSTD_DEFAULTS
config TARGET_X240
bool "Support Allied Telesis x240"
select ALLEYCAT_5
imply BOOTSTD_DEFAULTS
config TARGET_DB_XC3_24G4XG
bool "Support DB-XC3-24G4XG"
@ -301,6 +308,7 @@ config SYS_BOARD
default "theadorable" if TARGET_THEADORABLE
default "a38x" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
default "x250" if TARGET_X250
default "x240" if TARGET_X240
default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
@ -325,6 +333,7 @@ config SYS_CONFIG_NAME
default "turris_mox" if TARGET_TURRIS_MOX
default "controlcenterdc" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
default "x250" if TARGET_X250
default "x240" if TARGET_X240
default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236
@ -349,6 +358,7 @@ config SYS_VENDOR
default "CZ.NIC" if TARGET_TURRIS_MOX
default "gdsys" if TARGET_CONTROLCENTERDC
default "alliedtelesis" if TARGET_X530
default "alliedtelesis" if TARGET_X250
default "alliedtelesis" if TARGET_X240
default "mikrotik" if TARGET_CRS3XX_98DX3236
default "Marvell" if TARGET_MVEBU_ALLEYCAT5

4
arch/x86/cpu/intel_common/cpu_from_spl.c
View file

@ -24,7 +24,9 @@ int arch_cpu_init(void)
int ret;
#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
gd->arch.hob_list = handoff_get();
struct spl_handoff *ho = gd->spl_handoff;
gd->arch.hob_list = ho->arch.hob_list;
#endif
ret = x86_cpu_reinit_f();

4
arch/x86/lib/fsp2/fsp_dram.c
View file

@ -59,7 +59,7 @@ int dram_init(void)
#endif
} else {
#if CONFIG_IS_ENABLED(HANDOFF)
struct spl_handoff *ho = handoff_get();
struct spl_handoff *ho = gd->spl_handoff;
if (!ho) {
log_debug("No SPL handoff found\n");
@ -82,7 +82,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
return gd->ram_size;
#if CONFIG_IS_ENABLED(HANDOFF)
struct spl_handoff *ho = handoff_get();
struct spl_handoff *ho = gd->spl_handoff;
log_debug("usable_ram_top = %lx\n", ho->arch.usable_ram_top);

20
board/Marvell/sheevaplug/sheevaplug.env Normal file
View file

@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2024 Tony Dinh <mibodhi@gmail.com>
*
* Environment variables configurations
*/
kernel_addr_r=0x800000
fdt_addr_r=0x2c00000
ramdisk_addr_r=0x01100000
scriptaddr=0x200000
fdtfile=CONFIG_DEFAULT_DEVICE_TREE.dtb
mtdparts=CONFIG_MTDPARTS_DEFAULT
console=ttyS0,115200
/* Standard Boot */
bootcmd=
bootflow scan -lb
failed=
echo CONFIG_SYS_BOARD boot failed - please check your image

7
board/alliedtelesis/x250/MAINTAINERS Normal file
View file

@ -0,0 +1,7 @@
X250 BOARD
M: Chris Packham <chris.packham@alliedtelesis.co.nz>
S: Maintained
F: board/alliedtelesis/x250/
F: arch/arm/dts/cn9130-atl-x250.dts
F: include/configs/x250.h
F: configs/x250_defconfig

6
board/alliedtelesis/x250/Makefile Normal file
View file

@ -0,0 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2024 Allied Telesis
#
obj-y += x250.o

19
board/alliedtelesis/x250/x250.c Normal file
View file

@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+
#include <config.h>
#include <asm/global_data.h>
#include <linux/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define DEVICE_BUS_SYNC_CTRL 0xF27004C8
int board_init(void)
{
gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
writel(0x00004001, DEVICE_BUS_SYNC_CTRL);
return 0;
}

2
board/armltd/vexpress64/Kconfig
View file

@ -16,8 +16,8 @@ config VEXPRESS64_BASE_MODEL
select VIRTIO_BLK if VIRTIO_MMIO
select VIRTIO_NET if VIRTIO_MMIO
select DM_ETH if VIRTIO_NET
imply DM_RTC
imply RTC_PL031
select DM_RTC if RTC_PL031
imply EFI_SET_TIME if DM_RTC
select LINUX_KERNEL_IMAGE_HEADER
select POSITION_INDEPENDENT

3
board/data_modul/common/common.c
View file

@ -47,6 +47,9 @@ u8 dmo_get_memcfg(void)
"dmo,ram-coding-gpios",
gpio, ARRAY_SIZE(gpio),
GPIOD_IS_IN);
if (ret < 0)
return BIT(2) | BIT(0);
for (i = 0; i < ret; i++)
memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i;

6
board/data_modul/imx8mm_edm_sbc/spl.c
View file

@ -61,8 +61,10 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
{
if (boot_dev_spl == MMC3_BOOT)
return BOOT_DEVICE_MMC2; /* eMMC */
else
else if (boot_dev_spl == MMC2_BOOT)
return BOOT_DEVICE_MMC1; /* SD */
else
return BOOT_DEVICE_BOARD;
}
void board_boot_order(u32 *spl_boot_list)
@ -76,7 +78,7 @@ void board_boot_order(u32 *spl_boot_list)
else
spl_boot_list[1] = BOOT_DEVICE_MMC1; /* SD */
spl_boot_list[2] = BOOT_DEVICE_UART; /* YModem */
spl_boot_list[2] = BOOT_DEVICE_BOARD; /* SDP */
spl_boot_list[3] = BOOT_DEVICE_NONE;
}

2
board/emulation/qemu-arm/qemu-arm.c
View file

@ -48,7 +48,7 @@ struct efi_fw_image fw_images[] = {
};
struct efi_capsule_update_info update_info = {
.num_images = ARRAY_SIZE(fw_images)
.num_images = ARRAY_SIZE(fw_images),
.images = fw_images,
};

0
board/freescale/t208xqds/README Executable file → Normal file
View file

6
cmd/sb.c
View file

@ -15,10 +15,8 @@ static int do_sb_handoff(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
#if CONFIG_IS_ENABLED(HANDOFF)
struct spl_handoff *handoff = handoff_get();
if (handoff)
printf("SPL handoff magic %lx\n", handoff->arch.magic);
if (gd->spl_handoff)
printf("SPL handoff magic %lx\n", gd->spl_handoff->arch.magic);
else
printf("SPL handoff info not received\n");

12
common/board_f.c
View file

@ -305,6 +305,17 @@ static int setup_mon_len(void)
return 0;
}
static int setup_spl_handoff(void)
{
#if CONFIG_IS_ENABLED(HANDOFF)
gd->spl_handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF,
sizeof(struct spl_handoff));
debug("Found SPL hand-off info %p\n", gd->spl_handoff);
#endif
return 0;
}
__weak int arch_cpu_init(void)
{
return 0;
@ -873,6 +884,7 @@ static const init_fnc_t init_sequence_f[] = {
initf_bootstage, /* uses its own timer, so does not need DM */
event_init,
bloblist_maybe_init,
setup_spl_handoff,
#if defined(CONFIG_CONSOLE_RECORD_INIT_F)
console_record_init,
#endif

9
common/board_r.c
View file

@ -152,6 +152,15 @@ static int initr_reloc_global_data(void)
*/
gd->env_addr += gd->reloc_off;
#endif
/*
* For CONFIG_OF_EMBED case the FDT is embedded into ELF, available by
* __dtb_dt_begin. After U-boot ELF self-relocation to RAM top address
* it is worth to update fdt_blob in global_data
*/
if (IS_ENABLED(CONFIG_OF_EMBED))
gd->fdt_blob = dtb_dt_embedded();
#ifdef CONFIG_EFI_LOADER
/*
* On the ARM architecture gd is mapped to a fixed register (r9 or x18).

12
common/init/handoff.c
View file

@ -5,7 +5,6 @@
* Copyright 2018 Google, Inc
*/
#include <bloblist.h>
#include <handoff.h>
#include <asm/global_data.h>
@ -39,14 +38,3 @@ void handoff_load_dram_banks(struct spl_handoff *ho)
bd->bi_dram[i].size = ho->ram_bank[i].size;
}
}
struct spl_handoff *handoff_get(void)
{
struct spl_handoff *handoff;
handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF,
sizeof(struct spl_handoff));
debug("Found SPL hand-off info %p\n", handoff);
return handoff;
}

1
common/spl/Kconfig
View file

@ -462,6 +462,7 @@ config SPL_CUSTOM_SYS_MALLOC_ADDR
config SPL_SYS_MALLOC_SIZE
hex "Size of the SPL malloc pool"
depends on SPL_SYS_MALLOC
default 0x180000 if BIOSEMU && RISCV
default 0x100000
config SPL_READ_ONLY

8
configs/bcm947622_defconfig
View file

@ -8,7 +8,7 @@ CONFIG_TARGET_BCM947622=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm947622"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm947622"
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM47622"
@ -16,6 +16,12 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

8
configs/bcm94912_defconfig
View file

@ -9,13 +9,19 @@ CONFIG_TARGET_BCM94912=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm94912"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm94912"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM4912"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

8
configs/bcm963146_defconfig
View file

@ -9,13 +9,19 @@ CONFIG_TARGET_BCM963146=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm963146"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm963146"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM63146"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

8
configs/bcm963158_defconfig
View file

@ -9,13 +9,19 @@ CONFIG_TARGET_BCM963158=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm963158"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm963158"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM63158"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

8
configs/bcm963178_defconfig
View file

@ -9,7 +9,7 @@ CONFIG_TARGET_BCM963178=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm963178"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm963178"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM63178"
@ -17,6 +17,12 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

8
configs/bcm96756_defconfig
View file

@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96756=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm96756"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96756"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM6756"
@ -17,6 +17,12 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

8
configs/bcm96813_defconfig
View file

@ -9,13 +9,19 @@ CONFIG_TARGET_BCM96813=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm96813"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96813"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM6813"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

8
configs/bcm96855_defconfig
View file

@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96855=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm96855"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96855"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM6855"
@ -17,6 +17,12 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

8
configs/bcm96856_defconfig
View file

@ -9,13 +9,19 @@ CONFIG_TARGET_BCM96856=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm96856"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96856"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM6856"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

8
configs/bcm96858_defconfig
View file

@ -9,13 +9,19 @@ CONFIG_TARGET_BCM96858=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm96858"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96858"
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM6858"
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

8
configs/bcm96878_defconfig
View file

@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96878=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
CONFIG_DEFAULT_DEVICE_TREE="bcm96878"
CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96878"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x01000000
CONFIG_IDENT_STRING=" Broadcom BCM6878"
@ -17,6 +17,12 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_NAND=y
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_CLK=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_BCMBCA=y

1
configs/dns325_defconfig
View file

@ -33,7 +33,6 @@ CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896k(u-boot),128k(u-boot-env),5m(kernel),-(rootfs)"

1
configs/dockstar_defconfig
View file

@ -33,7 +33,6 @@ CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),-(root)"

1
configs/ds414_defconfig
View file

@ -49,7 +49,6 @@ CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
CONFIG_ENV_OVERWRITE=y

2
configs/e850-96_defconfig
View file

@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARM_SMCCC=y
CONFIG_ARCH_EXYNOS=y
CONFIG_TEXT_BASE=0xf8800000
CONFIG_SYS_MALLOC_LEN=0x81f000
@ -9,6 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000
CONFIG_DEFAULT_DEVICE_TREE="exynos/exynos850-e850-96"
CONFIG_SYS_LOAD_ADDR=0x80000000
# CONFIG_PSCI_RESET is not set
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_AUTOBOOT is not set
# CONFIG_DISPLAY_CPUINFO is not set

1
configs/goflexhome_defconfig
View file

@ -35,7 +35,6 @@ CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),6M(uImage),-(root)"

1
configs/guruplug_defconfig
View file

@ -35,7 +35,6 @@ CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896K(uboot),128K(uboot_env),-@1M(root)"

1
configs/iconnect_defconfig
View file

@ -35,7 +35,6 @@ CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x80000@0x0(uboot),0x20000@0x80000(uboot_env),-@0xa0000(rootfs)"

221
configs/imx8m_data_modul.config Normal file
View file

@ -0,0 +1,221 @@
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_INPUT is not set
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
# CONFIG_SPL_DM_USB is not set
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_ARCH_IMX8M=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_ARM=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_BKOPS_ENABLE=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_BTRFS=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_CAT=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_DHCP6=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_FS_UUID=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GETTIME=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_I2C=y
CONFIG_CMD_KASLRSEED=y
CONFIG_CMD_LSBLK=y
CONFIG_CMD_MBR=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MII=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_CMD_PART=y
CONFIG_CMD_PING=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_PXE=y
CONFIG_CMD_READ=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_SMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_UUID=y
CONFIG_CMD_WGET=y
CONFIG_CMD_XXD=y
CONFIG_CONSOLE_MUX=y
CONFIG_CRC32_VERIFY=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x30880000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DFU_MMC=y
CONFIG_DFU_MTD=y
CONFIG_DFU_RAM=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DM_ETH_PHY=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_DM_MDIO=y
CONFIG_DM_MTD=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RESET=y
CONFIG_DM_RNG=y
CONFIG_DM_RTC=y
CONFIG_DM_SERIAL=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_THERMAL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_OFFSET=0xFFFC0000
CONFIG_ENV_OFFSET_REDUND=0xFFFC0000
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
CONFIG_FASTBOOT_BUF_SIZE=0x20000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FEC_MXC=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FSL_CAAM=y
CONFIG_FSL_USDHC=y
CONFIG_GPIO_HOG=y
CONFIG_HASH_VERIFY=y
CONFIG_HUSH_PARSER=y
CONFIG_I2C_EEPROM=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_IMX_BOOTAUX=y
CONFIG_IMX_TMU=y
CONFIG_IMX_WATCHDOG=y
CONFIG_IPV6=y
CONFIG_IP_DEFRAG=y
CONFIG_MD5SUM_VERIFY=y
CONFIG_MII=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_SPEED_MODE_SET=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MTD=y
CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
CONFIG_MXC_GPIO=y
CONFIG_MXC_SPI=y
CONFIG_MXC_UART=y
CONFIG_NETCONSOLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_OF_CONTROL=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_POWER_DOMAIN=y
CONFIG_PROT_TCP_SACK=y
CONFIG_REGMAP=y
CONFIG_RGMII=y
CONFIG_RTC_M41T62=y
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SHA1SUM_VERIFY=y
CONFIG_SPI=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPL=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_GPIO=y
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_I2C=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_MMC=y
CONFIG_SPL_MMC_IO_VOLTAGE=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_PINCTRL=y
CONFIG_SPL_POWER=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_SYSRESET=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYSCON=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
CONFIG_SYS_EEPROM_SIZE=16384
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SYS_PBSIZE=2081
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_TEXT_BASE=0x40200000
CONFIG_TFTP_TSIZE=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_HUB_USB251XB=y
CONFIG_USB_STORAGE=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_USE_PREBOOT=y
CONFIG_VERSION_VARIABLE=y

273
configs/imx8mm_data_modul_edm_sbc_defconfig
View file

@ -1,242 +1,39 @@
#include <configs/imx8m_data_modul.config>
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xFFFC0000
CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-data-modul-edm-sbc"
CONFIG_TARGET_IMX8MM_DATA_MODUL_EDM_SBC=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
CONFIG_SPL_STACK=0x920000
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_SYS_LOAD_ADDR=0x60000000
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0xFFFC0000
CONFIG_IMX_BOOTAUX=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="run dmo_preboot"
CONFIG_DEFAULT_FDT_FILE="imx8mm-data-modul-edm-sbc.dtb"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_EEPROM_SIZE=16384
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
CONFIG_CMD_MD5SUM=y
CONFIG_MD5SUM_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_SHA1SUM=y
CONFIG_SHA1SUM_VERIFY=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_I2C=y
CONFIG_CMD_LSBLK=y
CONFIG_CMD_MBR=y
CONFIG_CMD_MMC=y
CONFIG_CMD_BKOPS_ENABLE=y
CONFIG_MMC_SPEED_MODE_SET=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PART=y
CONFIG_CMD_READ=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CAT=y
CONFIG_CMD_XXD=y
CONFIG_CMD_DHCP6=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_WGET=y
CONFIG_CMD_PXE=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_GETTIME=y
CONFIG_CMD_KASLRSEED=y
CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_FS_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_TSIZE=y
CONFIG_PROT_TCP_SACK=y
CONFIG_IPV6=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
CONFIG_FSL_CAAM=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_MTD=y
CONFIG_DFU_RAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
CONFIG_FASTBOOT_BUF_SIZE=0x20000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_GPIO_HOG=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
# CONFIG_INPUT is not set
CONFIG_USB_HUB_USB251XB=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_SPL_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_BD71837=y
CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_BD71837=y
CONFIG_SPL_DM_REGULATOR_BD71837=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RNG=y
CONFIG_DM_RTC=y
CONFIG_RTC_M41T62=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_TMU=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_FUNCTION_ACM=y
CONFIG_IMX_WATCHDOG=y
CONFIG_CLK_IMX8MM=y
CONFIG_CMD_PCI=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-data-modul-edm-sbc"
CONFIG_DEFAULT_FDT_FILE="imx8mm-data-modul-edm-sbc.dtb"
CONFIG_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR_BD71837=y
CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg"
CONFIG_NVME_PCI=y
CONFIG_PCI=y
CONFIG_PCIE_DW_IMX=y
CONFIG_PHY=y
CONFIG_PHYLIB=y
CONFIG_PHY_IMX8M_PCIE=y
CONFIG_PREBOOT="run dmo_preboot"
CONFIG_SDP_LOADADDR=0x60000000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_MAX_SIZE=0x30000
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_SPL_DM_REGULATOR_BD71837=y
CONFIG_SPL_DM_USB=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
CONFIG_SPL_LEGACY_IMAGE_FORMAT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_STACK=0x920000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SYS_LOAD_ADDR=0x60000000

293
configs/imx8mp_data_modul_edm_sbc_defconfig
View file

@ -1,271 +1,54 @@
#include <configs/imx8m_data_modul.config>
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_OFFSET=0xFFFC0000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-data-modul-edm-sbc"
CONFIG_TARGET_IMX8MP_DATA_MODUL_EDM_SBC=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
CONFIG_SPL_STACK=0x96fc00
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x96fc00
CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_DEBUG_UART_BASE=0x30880000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_ENV_OFFSET_REDUND=0xFFFC0000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset"
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="imx8mp-data-modul-edm-sbc.dtb"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2081
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_EEPROM_SIZE=16384
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
CONFIG_CMD_MD5SUM=y
CONFIG_MD5SUM_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_SHA1SUM=y
CONFIG_SHA1SUM_VERIFY=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_I2C=y
CONFIG_CMD_LSBLK=y
CONFIG_CMD_MBR=y
CONFIG_CMD_MMC=y
CONFIG_CMD_BKOPS_ENABLE=y
CONFIG_MMC_SPEED_MODE_SET=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PART=y
CONFIG_CMD_READ=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CAT=y
CONFIG_CMD_XXD=y
CONFIG_CMD_DHCP6=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_WGET=y
CONFIG_CMD_PXE=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_GETTIME=y
CONFIG_CMD_KASLRSEED=y
CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_FS_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_TSIZE=y
CONFIG_PROT_TCP_SACK=y
CONFIG_IPV6=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
CONFIG_FSL_CAAM=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-data-modul-edm-sbc"
CONFIG_DEFAULT_FDT_FILE="imx8mp-data-modul-edm-sbc.dtb"
CONFIG_DM_PMIC_PCA9450=y
CONFIG_DM_REGULATOR_PCA9450=y
CONFIG_DM_USB_GADGET=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
CONFIG_IMX8M_DRAM_INLINE_ECC=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_MTD=y
CONFIG_DFU_RAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
CONFIG_FASTBOOT_BUF_SIZE=0x20000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_GPIO_HOG=y
CONFIG_SPL_GPIO_HOG=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
# CONFIG_INPUT is not set
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_USB_HUB_USB251XB=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_SPL_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SPL_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ANEG_TIMEOUT=20000
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PCA9450=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_SPL_BSS_START_ADDR=0x96fc00
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000
CONFIG_SPL_DM_PMIC_PCA9450=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PCA9450=y
CONFIG_SPL_DM_REGULATOR_PCA9450=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RNG=y
CONFIG_DM_RTC=y
CONFIG_RTC_M41T62=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_TMU=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SPL_DM_SPI=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_GPIO_HOG=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_MMC_UHS_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_STACK=0x96fc00
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Data Modul"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETH_CDC=y
CONFIG_IMX_WATCHDOG=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
CONFIG_USB_XHCI_HCD=y

3
configs/nas220_defconfig
View file

@ -34,7 +34,6 @@ CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xa0000@0x0(uboot),0x010000@0xa0000(env),0x500000@0xc0000(uimage),0x1a40000@0x5c0000(rootfs)"
@ -66,5 +65,3 @@ CONFIG_SYS_NS16550_REG_SIZE=-4
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_NAND=y

1
configs/nsa310s_defconfig
View file

@ -30,7 +30,6 @@ CONFIG_CMD_NAND=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(root)"

3
configs/nsa325_defconfig
View file

@ -42,7 +42,6 @@ CONFIG_CMD_USB=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DNS=y
# CONFIG_CMD_BLOCK_CACHE is not set
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x100000(uboot),0x80000(stock_uboot_env),0x80000(key_store),0x80000(info),0xA00000(etc),0xA00000(kernel_1),0x2FC0000(rootfs1),0xA00000(kernel_2),0x2FC0000(rootfs2)"
@ -73,6 +72,4 @@ CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_NAND=y
CONFIG_UBIFS_SILENCE_MSG=y

2
configs/phycore_am62x_a53_defconfig
View file

@ -71,8 +71,8 @@ CONFIG_CMD_RTC=y
CONFIG_CMD_SMC=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_OF_OVERLAY_LIST="ti/k3-am6xx-phycore-disable-spi-nor ti/k3-am6xx-phycore-disable-rtc ti/k3-am6xx-phycore-disable-eth-phy ti/k3-am6xx-phycore-qspi-nor"
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y

1
configs/pogo_e02_defconfig
View file

@ -32,7 +32,6 @@ CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1M(u-boot),4M(uImage),32M(rootfs),-(data)"

3
configs/pogo_v4_defconfig
View file

@ -41,7 +41,6 @@ CONFIG_CMD_USB=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_DNS=y
# CONFIG_CMD_BLOCK_CACHE is not set
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:2M(u-boot),3M(uImage),3M(uImage2),8M(failsafe),112M(root)"
@ -73,6 +72,4 @@ CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_USB_EHCI_HCD=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_NAND=y
CONFIG_UBIFS_SILENCE_MSG=y

1
configs/qcom_defconfig
View file

@ -129,4 +129,3 @@ CONFIG_VIDEO_FONT_16X32=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_NO_FB_CLEAR=y
CONFIG_VIDEO_SIMPLE=y
CONFIG_HEXDUMP=y

1
configs/qemu_arm64_defconfig
View file

@ -3,7 +3,6 @@ CONFIG_POSITION_INDEPENDENT=y
CONFIG_ARCH_QEMU=y
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000

1
configs/qemu_arm_defconfig
View file

@ -3,7 +3,6 @@ CONFIG_ARM_SMCCC=y
CONFIG_ARCH_QEMU=y
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200000
CONFIG_ENV_SIZE=0x40000
CONFIG_ENV_SECT_SIZE=0x40000

16
configs/sheevaplug_defconfig
View file

@ -16,16 +16,14 @@ CONFIG_ENV_OFFSET=0x80000
CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-sheevaplug"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_IDENT_STRING="\nMarvell-Sheevaplug"
CONFIG_LTO=y
CONFIG_HAS_BOARD_SIZE_LIMIT=y
CONFIG_BOARD_SIZE_LIMIT=524288
CONFIG_BOOTSTD_FULL=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; bootm 0x6400000;"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
@ -35,19 +33,10 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_JFFS2=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=orion_nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
@ -68,6 +57,5 @@ CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LZMA=y
CONFIG_BZIP2=y

2
configs/sifive_unmatched_defconfig
View file

@ -42,6 +42,7 @@ CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_PWM=y
@ -58,6 +59,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x54
CONFIG_SPI_FLASH_ISSI=y
CONFIG_E1000=y
CONFIG_NVME_PCI=y
CONFIG_PCI_REGION_MULTI_ENTRY=y
CONFIG_PCIE_DW_SIFIVE=y
CONFIG_SCSI=y
CONFIG_USB=y

8
configs/x240_defconfig
View file

@ -27,16 +27,12 @@ CONFIG_CMD_PCI=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_IPV6=y
CONFIG_CLK=y
CONFIG_CLK_MVEBU=y
CONFIG_GPIO_HOG=y
@ -74,7 +70,6 @@ CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
@ -83,3 +78,4 @@ CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
# CONFIG_FAT_WRITE is not set
# CONFIG_SMBIOS is not set
# CONFIG_TOOLS_MKEFICAPSULE is not set

104
configs/x250_defconfig Normal file
View file

@ -0,0 +1,104 @@
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_MVEBU=y
CONFIG_TEXT_BASE=0x00000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
CONFIG_TARGET_X250=y
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xf80000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="cn9130-atl-x250"
CONFIG_SYS_LOAD_ADDR=0x10000000
CONFIG_DEBUG_UART_BASE=0xf0512000
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run distro_bootcmd"
CONFIG_USE_PREBOOT=y
CONFIG_SPL_SILENT_CONSOLE=y
CONFIG_TPL_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_UBI=y
CONFIG_MAC_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
CONFIG_IPV6=y
CONFIG_SYS_64BIT_LBA=y
CONFIG_GPIO_HOG=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_INPUT is not set
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_PXA3XX=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MVPP2=y
CONFIG_NVME_PCI=y
CONFIG_PCIE_DW_MVEBU=y
CONFIG_PHY=y
CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_8K=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
CONFIG_RTC_MAX313XX=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
# CONFIG_TOOLS_MKEFICAPSULE is not set

2
configs/x530_defconfig
View file

@ -65,6 +65,7 @@ CONFIG_CMD_UBI=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ARP_TIMEOUT=200
CONFIG_NET_RETRY_COUNT=50
CONFIG_IPV6=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
@ -95,3 +96,4 @@ CONFIG_USB_ETHER_ASIX88179=y
CONFIG_WDT=y
CONFIG_WDT_ORION=y
CONFIG_SPL_TINY_MEMSET=y
# CONFIG_TOOLS_MKEFICAPSULE is not set

2
doc/develop/release_cycle.rst
View file

@ -73,7 +73,7 @@ For the next scheduled release, release candidates were made on::
* U-Boot v2025.01-rc3 was released on Mon 25 November 2024.
.. * U-Boot v2025.01-rc4 was released on Mon 09 December 2024.
* U-Boot v2025.01-rc4 was released on Mon 09 December 2024.
.. * U-Boot v2025.01-rc5 was released on Mon 23 December 2024.

8
drivers/clk/renesas/rzg2l-cpg.c
View file

@ -69,7 +69,15 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
dev_dbg(clk->dev, "%s %s clock %u\n", enable ? "enable" : "disable",
is_mod_clk(clk->id) ? "module" : "core", cpg_clk_id);
if (!is_mod_clk(clk->id)) {
/*
* Non-module clocks are always on. Ignore attempts to enable
* them and reject attempts to disable them.
*/
if (enable)
return 0;
dev_err(clk->dev, "ID %lu is not a module clock\n", clk->id);
return -EINVAL;
}

3
drivers/clk/rockchip/clk_rk3399.c
View file

@ -8,7 +8,6 @@
#include <dm.h>
#include <dt-structs.h>
#include <errno.h>
#include <handoff.h>
#include <log.h>
#include <malloc.h>
#include <mapmem.h>
@ -1468,7 +1467,7 @@ static int rk3399_clk_probe(struct udevice *dev)
init_clocks = true;
#elif CONFIG_IS_ENABLED(HANDOFF)
if (!(gd->flags & GD_FLG_RELOC)) {
if (!handoff_get())
if (!(gd->spl_handoff))
init_clocks = true;
}
#endif

3
drivers/fastboot/fb_getvar.c
View file

@ -230,7 +230,8 @@ static void __maybe_unused getvar_partition_type(char *part_name, char *response
if (r >= 0) {
r = fs_set_blk_dev_with_part(dev_desc, r);
if (r < 0)
fastboot_fail("failed to set partition", response);
/* If we don't know then just default to raw */
fastboot_okay("raw", response);
else
fastboot_okay(fs_get_type_name(), response);
}

24
drivers/mtd/nand/raw/Kconfig
View file

@ -133,36 +133,12 @@ config NAND_BRCMNAND_6368
help
Enable support for broadcom nand driver on bcm6368.
config NAND_BRCMNAND_6753
bool "Support Broadcom NAND controller on bcm6753"
depends on NAND_BRCMNAND && BCM6855
help
Enable support for broadcom nand driver on bcm6753.
config NAND_BRCMNAND_68360
bool "Support Broadcom NAND controller on bcm68360"
depends on NAND_BRCMNAND && BCM6856
help
Enable support for broadcom nand driver on bcm68360.
config NAND_BRCMNAND_6838
bool "Support Broadcom NAND controller on bcm6838"
depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
help
Enable support for broadcom nand driver on bcm6838.
config NAND_BRCMNAND_6858
bool "Support Broadcom NAND controller on bcm6858"
depends on NAND_BRCMNAND && BCM6858
help
Enable support for broadcom nand driver on bcm6858.
config NAND_BRCMNAND_63158
bool "Support Broadcom NAND controller on bcm63158"
depends on NAND_BRCMNAND && BCM63158
help
Enable support for broadcom nand driver on bcm63158.
config NAND_BRCMNAND_IPROC
bool "Support Broadcom NAND controller on the iproc family"
depends on NAND_BRCMNAND

Some files were not shown because too many files have changed in this diff Show more