From e5565c24bb49f477c4326d2b5275ed88b50af1ef Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Tue, 10 Sep 2024 20:37:18 +0200 Subject: [PATCH 01/57] pinctrl: exynos: fix type of count integer unsigned int count is used to capture return of dev_read_string_count. When an error occurs dev_read_string_count returns -ve, which can hence not be handled correctly. Use int instead of unsigned int so that errors are detected. Fixes: 16ca80adc551 ("pinctrl: Add pinctrl driver support for Exynos7420 SoC") Signed-off-by: Henrik Grimler Signed-off-by: Minkyu Kang --- drivers/pinctrl/exynos/pinctrl-exynos.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c b/drivers/pinctrl/exynos/pinctrl-exynos.c index b393127c642..b37282fa9d6 100644 --- a/drivers/pinctrl/exynos/pinctrl-exynos.c +++ b/drivers/pinctrl/exynos/pinctrl-exynos.c @@ -114,8 +114,8 @@ static void exynos_pinctrl_set_pincfg(unsigned long reg_base, u32 pin_num, int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config) { struct exynos_pinctrl_priv *priv = dev_get_priv(dev); - unsigned int count, idx; - unsigned int pinvals[PINCFG_TYPE_NUM]; + int count; + unsigned int idx, pinvals[PINCFG_TYPE_NUM]; /* * refer to the following document for the pinctrl bindings From 57e77dc80e082b11f6fc2c9c5dd9ec9330a5a1a6 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 30 Oct 2024 15:46:27 -0500 Subject: [PATCH 02/57] arm: dts: e850-96: Remove TRNG node from appended dts Commit 136b7b6d2e98 ("Subtree merge tag 'v6.11-dts' of dts repo [1] into dts/upstream") updates the upstream dts for E850-96 board, bringing upstream TRNG node. There is no need to keep TRNG node in appended dts anymore, so remove it. Tested on E850-96 board by running 'rng' command in U-Boot shell. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- arch/arm/dts/exynos850-e850-96-u-boot.dtsi | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi index 3aa5d8bb10d..6d7148f7264 100644 --- a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi +++ b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi @@ -3,17 +3,6 @@ * Copyright (c) 2023 Linaro Ltd. */ -&soc { - /* TODO: Remove this node once it appears in upstream dts */ - trng: rng@12081400 { - compatible = "samsung,exynos850-trng"; - reg = <0x12081400 0x100>; - clocks = <&cmu_core CLK_GOUT_SSS_ACLK>, - <&cmu_core CLK_GOUT_SSS_PCLK>; - clock-names = "secss", "pclk"; - }; -}; - &pmu_system_controller { bootph-all; samsung,uart-debug-1; From 06b8aafd6810d86f37d5b1cd9c1966f1e42403ed Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Wed, 13 Nov 2024 06:05:59 +0100 Subject: [PATCH 03/57] fastboot: properly handle unknown partition type In getvar_partition_type() we attempt to find a filesystem driver for the partition (of the list of driver enabled in U-Boot), on failure we return the error to fastboot and completely bail out of the operation. However, this should not be a failure, instead we should just default to "raw". This allows commands like "fastboot format:ext4 userdata" to work if userdata didn't already have an ext4 partition table (or if FS_EXT4 is disabled in U-Boot), as failing to determine the current partition type is not an error in this case. Signed-off-by: Caleb Connolly Reviewed-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20241113050607.1850472-1-caleb.connolly@linaro.org Signed-off-by: Mattijs Korpershoek --- drivers/fastboot/fb_getvar.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c index 93cbd598e02..9c2ce65a4e5 100644 --- a/drivers/fastboot/fb_getvar.c +++ b/drivers/fastboot/fb_getvar.c @@ -230,7 +230,8 @@ static void __maybe_unused getvar_partition_type(char *part_name, char *response if (r >= 0) { r = fs_set_blk_dev_with_part(dev_desc, r); if (r < 0) - fastboot_fail("failed to set partition", response); + /* If we don't know then just default to raw */ + fastboot_okay("raw", response); else fastboot_okay(fs_get_type_name(), response); } From 35d967f5a8219adc47628247a98c302b1870313e Mon Sep 17 00:00:00 2001 From: Ion Agorria Date: Tue, 26 Nov 2024 09:29:56 +0200 Subject: [PATCH 04/57] usb: ci_udc: don't use "advance" feature when setting address In the older USB controllers like for example in ChipIdea controller used by the Tegra 2 the "USBADRA: Device Address Advance" bitflag does not exist, so the new device address set during SET_ADDRESS can't be deferred by hardware, which causes the host to not recognize the device and give an error. Instead store it until ep completes to apply the change into the hw register as Linux kernel does. This should fix regression on old and and be compatible with newer controllers. Inspired by: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ef15e5490edc7edf808d3477ab32e0e320792f65 Signed-off-by: Ion Agorria Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20241126072956.64778-2-clamor95@gmail.com Signed-off-by: Mattijs Korpershoek --- drivers/usb/gadget/ci_udc.c | 24 +++++++++++++++++++++++- drivers/usb/gadget/ci_udc.h | 1 + 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index bbe03cfff1f..4bff75da759 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -649,12 +649,30 @@ static void flip_ep0_direction(void) } } +/* + * This function explicitly sets the address, without the "USBADRA" (advance) + * feature, which is not supported by older versions of the controller. + */ +static void ci_set_address(struct ci_udc *udc, u8 address) +{ + DBG("%s %x\n", __func__, address); + writel(address << 25, &udc->devaddr); +} + static void handle_ep_complete(struct ci_ep *ci_ep) { struct ept_queue_item *item, *next_td; int num, in, len, j; struct ci_req *ci_req; + /* Set the device address that was previously sent by SET_ADDRESS */ + if (controller.next_device_address != 0) { + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + + ci_set_address(udc, controller.next_device_address); + controller.next_device_address = 0; + } + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; item = ci_get_qtd(num, in); @@ -783,7 +801,7 @@ static void handle_setup(void) * write address delayed (will take effect * after the next IN txn) */ - writel((r.wValue << 25) | (1 << 24), &udc->devaddr); + controller.next_device_address = r.wValue; req->length = 0; usb_ep_queue(controller.gadget.ep0, req, 0); return; @@ -814,6 +832,9 @@ static void stop_activity(void) int i, num, in; struct ept_queue_head *head; struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + + ci_set_address(udc, 0); + writel(readl(&udc->epcomp), &udc->epcomp); #ifdef CONFIG_CI_UDC_HAS_HOSTPC writel(readl(&udc->epsetupstat), &udc->epsetupstat); @@ -934,6 +955,7 @@ static int ci_pullup(struct usb_gadget *gadget, int is_on) struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; if (is_on) { /* RESET */ + controller.next_device_address = 0; writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd); udelay(200); diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h index bea2f9f3fe3..807f2084c1e 100644 --- a/drivers/usb/gadget/ci_udc.h +++ b/drivers/usb/gadget/ci_udc.h @@ -105,6 +105,7 @@ struct ci_drv { struct ept_queue_head *epts; uint8_t *items_mem; struct ci_ep ep[NUM_ENDPOINTS]; + u8 next_device_address; }; struct ept_queue_head { From 325ac6c1e7facd67b91eb8ada12b49f648063942 Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Mon, 18 Nov 2024 11:34:59 -0800 Subject: [PATCH 05/57] arm: mvebu: Disable JFFS2 support for Kirkwood and Armada XP boards These boards don't use JFFS2 file system for booting so remove it. Ref: https://lore.kernel.org/u-boot/20241114233005.GN3600562@bill-the-cat/T/#t Signed-off-by: Tony Dinh Acked-by: Phil Sutter Reviewed-by: Stefan Roese --- configs/dns325_defconfig | 1 - configs/dockstar_defconfig | 1 - configs/ds414_defconfig | 1 - configs/goflexhome_defconfig | 1 - configs/guruplug_defconfig | 1 - configs/iconnect_defconfig | 1 - configs/nas220_defconfig | 3 --- configs/nsa310s_defconfig | 1 - configs/nsa325_defconfig | 3 --- configs/pogo_e02_defconfig | 1 - configs/pogo_v4_defconfig | 3 --- 11 files changed, 17 deletions(-) diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index 323e2f5d4c8..1ba02e0595f 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -33,7 +33,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896k(u-boot),128k(u-boot-env),5m(kernel),-(rootfs)" diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index e35ca165d0f..941156750ac 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -33,7 +33,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),-(root)" diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index 25e5be3ba7d..44e9b176827 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -49,7 +49,6 @@ CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index af758fcc431..add4a24a31d 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1m(uboot),6M(uImage),-(root)" diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index 0fab4c38e0e..540b9184b38 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:896K(uboot),128K(uboot_env),-@1M(root)" diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index 9d195e1cf2d..6ee40e380b2 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x80000@0x0(uboot),0x20000@0x80000(uboot_env),-@0xa0000(rootfs)" diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index 783879d4eec..ca70ee96379 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xa0000@0x0(uboot),0x010000@0xa0000(env),0x500000@0xc0000(uimage),0x1a40000@0x5c0000(rootfs)" @@ -66,5 +65,3 @@ CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_NAND=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index f6718350d58..9a42c391556 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -30,7 +30,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(root)" diff --git a/configs/nsa325_defconfig b/configs/nsa325_defconfig index c4235eecfb5..ab9316340d8 100644 --- a/configs/nsa325_defconfig +++ b/configs/nsa325_defconfig @@ -42,7 +42,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y # CONFIG_CMD_BLOCK_CACHE is not set -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x100000(uboot),0x80000(stock_uboot_env),0x80000(key_store),0x80000(info),0xA00000(etc),0xA00000(kernel_1),0x2FC0000(rootfs1),0xA00000(kernel_2),0x2FC0000(rootfs2)" @@ -73,6 +72,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y CONFIG_USB_EHCI_HCD=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_NAND=y CONFIG_UBIFS_SILENCE_MSG=y diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index 50103f375a1..50c92925506 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -32,7 +32,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:1M(u-boot),4M(uImage),32M(rootfs),-(data)" diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig index fb8036a75e1..03b4fd9b2fc 100644 --- a/configs/pogo_v4_defconfig +++ b/configs/pogo_v4_defconfig @@ -41,7 +41,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y # CONFIG_CMD_BLOCK_CACHE is not set -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:2M(u-boot),3M(uImage),3M(uImage2),8M(failsafe),112M(root)" @@ -73,6 +72,4 @@ CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y CONFIG_USB_EHCI_HCD=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_NAND=y CONFIG_UBIFS_SILENCE_MSG=y From 96ca3147981ab1bdd10426a3d2792e1d99bad321 Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Thu, 21 Nov 2024 11:02:27 -0800 Subject: [PATCH 06/57] arm: kirkwood: Enable bootstd for Sheevaplug board Enable bootstd for Sheevaplug board. Remove JFFS2 support. See JFFS2 Vulnerability[1]. Enable LTO to keep board size within limit. Move default envs to text-base environment [1] https://lore.kernel.org/u-boot/20241114233005.GN3600562@bill-the-cat/T/#m2fc25da1d2c019bc3cd8676991fdd64b8a21aa9b Signed-off-by: Tony Dinh Reviewed-by: Stefan Roese --- board/Marvell/sheevaplug/sheevaplug.env | 20 ++++++++++++++++++++ configs/sheevaplug_defconfig | 16 ++-------------- include/configs/sheevaplug.h | 9 --------- 3 files changed, 22 insertions(+), 23 deletions(-) create mode 100644 board/Marvell/sheevaplug/sheevaplug.env diff --git a/board/Marvell/sheevaplug/sheevaplug.env b/board/Marvell/sheevaplug/sheevaplug.env new file mode 100644 index 00000000000..bcd62dbeb73 --- /dev/null +++ b/board/Marvell/sheevaplug/sheevaplug.env @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2024 Tony Dinh + * + * Environment variables configurations + */ + +kernel_addr_r=0x800000 +fdt_addr_r=0x2c00000 +ramdisk_addr_r=0x01100000 +scriptaddr=0x200000 +fdtfile=CONFIG_DEFAULT_DEVICE_TREE.dtb +mtdparts=CONFIG_MTDPARTS_DEFAULT +console=ttyS0,115200 + +/* Standard Boot */ +bootcmd= + bootflow scan -lb +failed= + echo CONFIG_SYS_BOARD boot failed - please check your image diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 9ac40b9e571..a7f6c73ecba 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -16,16 +16,14 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-sheevaplug" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_IDENT_STRING="\nMarvell-Sheevaplug" +CONFIG_LTO=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=524288 +CONFIG_BOOTSTD_FULL=y CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; bootm 0x6400000;" CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set @@ -35,19 +33,10 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_SATA=y CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)" CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y @@ -68,6 +57,5 @@ CONFIG_DM_RTC=y CONFIG_RTC_MV=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_LZMA=y CONFIG_BZIP2=y diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 4e0b3c663c7..0a5f23e4c88 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -12,13 +12,4 @@ #include "mv-common.h" -/* - * Environment variables configurations - */ -#define CFG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 mtdparts=" CONFIG_MTDPARTS_DEFAULT \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" - #endif /* _CONFIG_SHEEVAPLUG_H */ From 3eef899b57fd2522a5d975b2957d2f2c0635a652 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 22 Nov 2024 13:30:15 +1300 Subject: [PATCH 07/57] arm: mvebu: x240: Use default baudrate table Remove CFG_SYS_BAUDRATE_TABLE as there's no reason not to use the defaults defined via config_fallbacks.h. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- include/configs/x240.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/x240.h b/include/configs/x240.h index 3601df588d5..bc66e4e3c8e 100644 --- a/include/configs/x240.h +++ b/include/configs/x240.h @@ -11,9 +11,6 @@ /* additions for new ARM relocation support */ #define CFG_SYS_SDRAM_BASE 0x200000000 -#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400, 460800, 921600 } - /* Default Env vars */ #define BOOT_TARGET_DEVICES(func) \ From 27b24887352bfcc360ccd14c44e4e9a767a9505a Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 22 Nov 2024 13:30:16 +1300 Subject: [PATCH 08/57] arm: mvebu: x240: Switch to standard boot Use standard boot instead of the distro boot scripts. Regenerate the board defconfig now that some options are selected automatically. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/Kconfig | 1 + configs/x240_defconfig | 6 ------ include/configs/x240.h | 9 ++------- 3 files changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index c1a1a333e6c..b61253e2d09 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -218,6 +218,7 @@ config TARGET_X530 config TARGET_X240 bool "Support Allied Telesis x240" select ALLEYCAT_5 + imply BOOTSTD_DEFAULTS config TARGET_DB_XC3_24G4XG bool "Support DB-XC3-24G4XG" diff --git a/configs/x240_defconfig b/configs/x240_defconfig index f930d28de2d..4fca1096e74 100644 --- a/configs/x240_defconfig +++ b/configs/x240_defconfig @@ -27,14 +27,9 @@ CONFIG_CMD_PCI=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_REGULATOR=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_CLK=y @@ -74,7 +69,6 @@ CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y diff --git a/include/configs/x240.h b/include/configs/x240.h index bc66e4e3c8e..05241f33d74 100644 --- a/include/configs/x240.h +++ b/include/configs/x240.h @@ -12,18 +12,13 @@ #define CFG_SYS_SDRAM_BASE 0x200000000 /* Default Env vars */ - -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) - -#include +#define BOOT_TARGETS "usb dhcp" #define CFG_EXTRA_ENV_SETTINGS \ - BOOTENV \ "kernel_addr_r=0x202000000\0" \ "fdt_addr_r=0x201000000\0" \ "ramdisk_addr_r=0x206000000\0" \ + "boot_targets=" BOOT_TARGETS "\0" \ "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" /* From cbbfa8d77828c754341295a6d865123309cfa011 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 22 Nov 2024 13:30:17 +1300 Subject: [PATCH 09/57] arm: mvebu: x240: Don't build mkeficapsule The x240 board doesn't use EFI and our toolchains don't include gnutls so disable the tool in the defconfig. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- configs/x240_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/x240_defconfig b/configs/x240_defconfig index 4fca1096e74..5e5b467b7ba 100644 --- a/configs/x240_defconfig +++ b/configs/x240_defconfig @@ -77,3 +77,4 @@ CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y # CONFIG_FAT_WRITE is not set # CONFIG_SMBIOS is not set +# CONFIG_TOOLS_MKEFICAPSULE is not set From b25b2d4f67e7add429594789f4a3b9ff8e6fa2ad Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 22 Nov 2024 13:30:18 +1300 Subject: [PATCH 10/57] arm: mvebu: x240: Enable IPV6 support Enable IPV6 support for the x240 board. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- configs/x240_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/x240_defconfig b/configs/x240_defconfig index 5e5b467b7ba..ff64916204c 100644 --- a/configs/x240_defconfig +++ b/configs/x240_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_TIME=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_IPV6=y CONFIG_CLK=y CONFIG_CLK_MVEBU=y CONFIG_GPIO_HOG=y From 1b46176532a514a3f38db5e401ecfde744344c7f Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 22 Nov 2024 13:30:19 +1300 Subject: [PATCH 11/57] arm: mvebu: x530: Remove dead comments As things have been moved to Kconfig there are a number of dead comments left over in x530.h. Remove them. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- include/configs/x530.h | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/include/configs/x530.h b/include/configs/x530.h index 982b1292873..c7bfd1de17c 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -18,30 +18,14 @@ #define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - /* NAND */ #define BBT_CUSTOM_SCAN #define BBT_CUSTOM_SCAN_PAGE 0 #define BBT_CUSTOM_SCAN_POSITION 2048 -/* SPI NOR flash default params, used by sf commands */ - #define MTDPARTS_MTDOOPS "errlog" -/* Partition support */ - -/* Additional FS support/configuration */ - -/* Environment in SPI NOR flash */ - -/* NAND */ - #include /* Keep device tree and initrd in low memory so the kernel can access them */ From c6b17af14227f5d3d9678b2e98163acd852e7b73 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 22 Nov 2024 13:30:20 +1300 Subject: [PATCH 12/57] arm: mvebu: x530: Don't build mkeficapsule The x530 board doesn't use EFI and our toolchains don't include gnutls so disable the tool in the defconfig. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- configs/x530_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/x530_defconfig b/configs/x530_defconfig index 89612be631e..a5b1cc3f8e8 100644 --- a/configs/x530_defconfig +++ b/configs/x530_defconfig @@ -95,3 +95,4 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_WDT=y CONFIG_WDT_ORION=y CONFIG_SPL_TINY_MEMSET=y +# CONFIG_TOOLS_MKEFICAPSULE is not set From f337b5aaad88a2fbb47a3c3350125807c10ec56a Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Fri, 22 Nov 2024 13:30:21 +1300 Subject: [PATCH 13/57] arm: mvebu: x530: Enable IPV6 support Enable IPV6 support for the x530 board. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- configs/x530_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/x530_defconfig b/configs/x530_defconfig index a5b1cc3f8e8..815370c90ec 100644 --- a/configs/x530_defconfig +++ b/configs/x530_defconfig @@ -65,6 +65,7 @@ CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 +CONFIG_IPV6=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y From 7446e29db54818324859126739c3477a15d25c36 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Tue, 26 Nov 2024 08:55:53 +1300 Subject: [PATCH 14/57] arm: mvebu: Add Allied Telesis x250 board The x250 and SE250 are series of 10G L2+ switches from Allied Telesis. There are a number of them in the range but as far as U-Boot is concerned all the CPU block components are the same so there's only one board defined. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/cn9130-atl-x250.dts | 274 +++++++++++++++++++++++++++ arch/arm/mach-mvebu/Kconfig | 9 + board/alliedtelesis/x250/MAINTAINERS | 7 + board/alliedtelesis/x250/Makefile | 6 + board/alliedtelesis/x250/x250.c | 19 ++ configs/x250_defconfig | 104 ++++++++++ include/configs/x250.h | 28 +++ 8 files changed, 449 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/cn9130-atl-x250.dts create mode 100644 board/alliedtelesis/x250/MAINTAINERS create mode 100644 board/alliedtelesis/x250/Makefile create mode 100644 board/alliedtelesis/x250/x250.c create mode 100644 configs/x250_defconfig create mode 100644 include/configs/x250.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 042282f3723..6ad59aeed5f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -190,7 +190,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ cn9130-crb-A.dtb \ cn9130-crb-B.dtb \ ac5-98dx35xx-rd.dtb \ - ac5-98dx35xx-atl-x240.dtb + ac5-98dx35xx-atl-x240.dtb \ + cn9130-atl-x250.dtb endif dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb diff --git a/arch/arm/dts/cn9130-atl-x250.dts b/arch/arm/dts/cn9130-atl-x250.dts new file mode 100644 index 00000000000..f2c82da9d14 --- /dev/null +++ b/arch/arm/dts/cn9130-atl-x250.dts @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Allied Telesis Labs + */ + +#include "cn9130.dtsi" + +/ { + model = "Allied Telesis x250"; + compatible = "alliedtelesis,x250", + "marvell,cn9130", + "marvell,armada-ap806-quad", + "marvell,armada-ap806"; + + aliases { + serial0 = &uart0; + i2c0 = &cp0_i2c0; + i2c1 = &cp0_i2c1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + fault { + label = "fault:red"; + gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; +}; + +/* + * AP related configuration + */ +&ap_pinctl { + /* AP_MPP Pins: + * GPIO & NC [0-6,9-10,12] + * UART0 [11,19] + * UART1 [7,8] + * Note: The x250-28XTm PT1 units has the console port wired + * to the second uart pins (UART1). This was fixed in all + * subsequent models. + * Here we choose to configure the pin control for both + * uarts to cater for either unit. + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 0 0 0 0 0 0 0 3 3 0 + 0 3 0 0 0 0 0 0 0 3 >; +}; + +&ap_gpio0 { + pp-reset { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + output-high; + line-name = "pp-reset"; + }; +}; + +/* + * CP related configuration + */ +&cp0_pinctl { + /* MPP Bus: + * [0-1] DEV + * [2-8] GPIO + * [9] DEV + * [10-12] GPIO + * [13] ND_RB + * [14] GPIO + * [15-28] DEV + * [29-30] GPIO + * [31] DEV + * [32-34] GPIO + * [35-36] I2C1 + * [37-38] I2C0 + * [39-55] GPIO + * [56-60] SPI + * [61-62] GPIO + */ + /* 0 1 2 3 4 5 6 7 8 9 */ + pin-func = < 1 1 0 0 0 0 0 0 0 1 + 0 0 0 2 0 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 0 + 0 1 0 0 0 2 2 2 2 0 + 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 6 6 6 6 + 6 0 0>; + + cp0_i2c0_pins: cp0-i2c-pins-0 { + marvell,pins = <37 38>; + marvell,function = <2>; + }; + + cp0_i2c0_gpio_pins: cp0-i2c-gpio-pins-0 { + marvell,pins = <37 38>; + marvell,function = <0>; + }; + + cp0_i2c1_pins: cp0-i2c-pins-1 { + marvell,pins = <35 36>; + marvell,function = <2>; + }; + + cp0_nand_pins: cp0-nand-pins { + marvell,pins = <0 1 9 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31>; + marvell,function = <1>; + }; + + cp0_nand_rb: cp0-nand-rb { + marvell,pins = <13>; + marvell,function = <2>; + }; + + cp0_spi0_pins: cp0-spi-pins-0 { + marvell,pins = <56 57 58 59 60>; + marvell,function = <6>; + }; +}; + +&cp0_comphy { + phy0 { + phy-type = ; + }; + + phy1 { + phy-type = ; + }; + + phy2 { + phy-type = ; + }; + + phy3 { + phy-type = ; + }; + + phy4 { + phy-type = ; + }; + + phy5 { + phy-type = ; + }; +}; + +&cp0_pcie0 { + num-lanes = <1>; + /* non-prefetchable memory */ + ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>; + status = "disabled"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + clock-frequency = <200000000>; +}; + +&cp0_utmi0 { + status = "okay"; +}; + +&cp0_usb3_0 { + status = "okay"; +}; + +&cp0_spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_spi0_pins>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; +}; + +&cp0_nand { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-timing-mode = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@user { + reg = <0x00000000 0x10000000>; + label = "user"; + }; + }; +}; + +&cp0_gpio0 +{ + nand-protect { + gpio-hog; + gpios = <29 GPIO_ACTIVE_LOW>; + output-low; + line-name = "nand-protect"; + }; +}; + +&cp0_gpio1 +{ + usb-en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-en"; + }; + + phy-reset { + gpio-hog; + gpios = <21 GPIO_ACTIVE_LOW>; + output-high; + line-name = "phy-reset"; + }; +}; + +&cp0_i2c0 { + status = "okay"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&cp0_i2c0_pins>; + pinctrl-1 = <&cp0_i2c0_gpio_pins>; + scl-gpios = <&cp0_gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&cp0_gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + mux@71 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9546"; + reg = <0x71>; + i2c-mux-idle-disconnect; + reset-gpios = <&cp0_gpio1 19 GPIO_ACTIVE_LOW>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + hwmon@2e { + compatible = "adi,adt7476"; + reg = <0x2e>; + }; + + rtc@68 { + compatible = "adi,max31331"; + reg = <0x68>; + }; + }; + }; +}; + +&cp0_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c1_pins>; +}; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index b61253e2d09..adb816982f8 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -215,6 +215,12 @@ config TARGET_X530 bool "Support Allied Telesis x530" select 88F6820 +config TARGET_X250 + bool "Support Allied Telesis x250" + select ARMADA_8K + imply SCSI + imply BOOTSTD_DEFAULTS + config TARGET_X240 bool "Support Allied Telesis x240" select ALLEYCAT_5 @@ -302,6 +308,7 @@ config SYS_BOARD default "theadorable" if TARGET_THEADORABLE default "a38x" if TARGET_CONTROLCENTERDC default "x530" if TARGET_X530 + default "x250" if TARGET_X250 default "x240" if TARGET_X240 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 @@ -326,6 +333,7 @@ config SYS_CONFIG_NAME default "turris_mox" if TARGET_TURRIS_MOX default "controlcenterdc" if TARGET_CONTROLCENTERDC default "x530" if TARGET_X530 + default "x250" if TARGET_X250 default "x240" if TARGET_X240 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG default "crs3xx-98dx3236" if TARGET_CRS3XX_98DX3236 @@ -350,6 +358,7 @@ config SYS_VENDOR default "CZ.NIC" if TARGET_TURRIS_MOX default "gdsys" if TARGET_CONTROLCENTERDC default "alliedtelesis" if TARGET_X530 + default "alliedtelesis" if TARGET_X250 default "alliedtelesis" if TARGET_X240 default "mikrotik" if TARGET_CRS3XX_98DX3236 default "Marvell" if TARGET_MVEBU_ALLEYCAT5 diff --git a/board/alliedtelesis/x250/MAINTAINERS b/board/alliedtelesis/x250/MAINTAINERS new file mode 100644 index 00000000000..8a74dbc68b6 --- /dev/null +++ b/board/alliedtelesis/x250/MAINTAINERS @@ -0,0 +1,7 @@ +X250 BOARD +M: Chris Packham +S: Maintained +F: board/alliedtelesis/x250/ +F: arch/arm/dts/cn9130-atl-x250.dts +F: include/configs/x250.h +F: configs/x250_defconfig diff --git a/board/alliedtelesis/x250/Makefile b/board/alliedtelesis/x250/Makefile new file mode 100644 index 00000000000..98e0ccedde4 --- /dev/null +++ b/board/alliedtelesis/x250/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Allied Telesis +# + +obj-y += x250.o diff --git a/board/alliedtelesis/x250/x250.c b/board/alliedtelesis/x250/x250.c new file mode 100644 index 00000000000..66c782698ff --- /dev/null +++ b/board/alliedtelesis/x250/x250.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define DEVICE_BUS_SYNC_CTRL 0xF27004C8 + +int board_init(void) +{ + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + + /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */ + writel(0x00004001, DEVICE_BUS_SYNC_CTRL); + + return 0; +} diff --git a/configs/x250_defconfig b/configs/x250_defconfig new file mode 100644 index 00000000000..dffe85bd6eb --- /dev/null +++ b/configs/x250_defconfig @@ -0,0 +1,104 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_MVEBU=y +CONFIG_TEXT_BASE=0x00000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000 +CONFIG_TARGET_X250=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xf80000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="cn9130-atl-x250" +CONFIG_SYS_LOAD_ADDR=0x10000000 +CONFIG_DEBUG_UART_BASE=0xf0512000 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd" +CONFIG_USE_PREBOOT=y +CONFIG_SPL_SILENT_CONSOLE=y +CONFIG_TPL_SILENT_CONSOLE=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_UBI=y +CONFIG_MAC_PARTITION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ARP_TIMEOUT=200 +CONFIG_NET_RETRY_COUNT=50 +CONFIG_IPV6=y +CONFIG_SYS_64BIT_LBA=y +CONFIG_GPIO_HOG=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +# CONFIG_INPUT is not set +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +# CONFIG_MMC is not set +CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_NAND_PXA3XX=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_GIGE=y +CONFIG_E1000=y +CONFIG_MVPP2=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_MVEBU=y +CONFIG_PHY=y +CONFIG_MVEBU_COMPHY_SUPPORT=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ARMADA_8K=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_RTC_MAX313XX=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_SYS_NS16550=y +CONFIG_KIRKWOOD_SPI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +# CONFIG_TOOLS_MKEFICAPSULE is not set diff --git a/include/configs/x250.h b/include/configs/x250.h new file mode 100644 index 00000000000..39f523fa6c4 --- /dev/null +++ b/include/configs/x250.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 Allied Telesis + */ + +#ifndef __X250_H_ +#define __X250_H_ + +/* + * High Level Configuration Options (easy to change) + */ +#define CFG_SYS_TCLK 250000000 /* 250MHz */ + +/* additions for new ARM relocation support */ +#define CFG_SYS_SDRAM_BASE 0x00000000 + +#define BOOT_TARGETS "usb scsi pxe dhcp" + +#define CFG_EXTRA_ENV_SETTINGS \ + "scriptaddr=0x6d00000\0" \ + "pxefile_addr_r=0x6e00000\0" \ + "fdt_addr_r=0x6f00000\0" \ + "kernel_addr_r=0x7000000\0" \ + "ramdisk_addr_r=0xa000000\0" \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "boot_targets=" BOOT_TARGETS "\0" + +#endif /* __X250_H_ */ From 3881c6b90350b0b04085ad46ef64989b43967eef Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 26 Nov 2024 08:10:18 -0600 Subject: [PATCH 15/57] configs: Resync with savedefconfig Rsync all defconfig files using qconfig.py Signed-off-by: Tom Rini --- configs/phycore_am62x_a53_defconfig | 2 +- configs/qcom_defconfig | 1 - configs/qemu_arm64_defconfig | 1 - configs/qemu_arm_defconfig | 1 - 4 files changed, 1 insertion(+), 4 deletions(-) diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 0b0cf176324..43b0dac5efd 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -71,8 +71,8 @@ CONFIG_CMD_RTC=y CONFIG_CMD_SMC=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_MULTI_DTB_FIT=y CONFIG_OF_OVERLAY_LIST="ti/k3-am6xx-phycore-disable-spi-nor ti/k3-am6xx-phycore-disable-rtc ti/k3-am6xx-phycore-disable-eth-phy ti/k3-am6xx-phycore-qspi-nor" +CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 30f7b1c773f..cd94315f176 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -129,4 +129,3 @@ CONFIG_VIDEO_FONT_16X32=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_NO_FB_CLEAR=y CONFIG_VIDEO_SIMPLE=y -CONFIG_HEXDUMP=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 8dffb91e93b..06ac6fed3bc 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -3,7 +3,6 @@ CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_QEMU=y CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index cc4f4540fd5..e164407d494 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -3,7 +3,6 @@ CONFIG_ARM_SMCCC=y CONFIG_ARCH_QEMU=y CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x40200000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 From a2fa53be4fae9f0da63f47363ce7cc80a6c8b67f Mon Sep 17 00:00:00 2001 From: david regan Date: Tue, 12 Nov 2024 22:27:12 -0800 Subject: [PATCH 16/57] mtd: nand: brcmnand: remove device specific nand driver files These device specific nand driver files can be removed because they are now replaced by a common driver bcmbca_nand.c Signed-off-by: david regan Reviewed-by: Linus Walleij Reviewed-by: William Zhang Reviewed-by: Anand Gore --- drivers/mtd/nand/raw/Kconfig | 24 ---- drivers/mtd/nand/raw/brcmnand/Makefile | 4 - drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c | 125 ------------------ drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c | 123 ----------------- drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c | 124 ----------------- drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c | 125 ------------------ 6 files changed, 525 deletions(-) delete mode 100644 drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c delete mode 100644 drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c delete mode 100644 drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c delete mode 100644 drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index c345fc1f1fb..609bdffbf77 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -133,36 +133,12 @@ config NAND_BRCMNAND_6368 help Enable support for broadcom nand driver on bcm6368. -config NAND_BRCMNAND_6753 - bool "Support Broadcom NAND controller on bcm6753" - depends on NAND_BRCMNAND && BCM6855 - help - Enable support for broadcom nand driver on bcm6753. - -config NAND_BRCMNAND_68360 - bool "Support Broadcom NAND controller on bcm68360" - depends on NAND_BRCMNAND && BCM6856 - help - Enable support for broadcom nand driver on bcm68360. - config NAND_BRCMNAND_6838 bool "Support Broadcom NAND controller on bcm6838" depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838 help Enable support for broadcom nand driver on bcm6838. -config NAND_BRCMNAND_6858 - bool "Support Broadcom NAND controller on bcm6858" - depends on NAND_BRCMNAND && BCM6858 - help - Enable support for broadcom nand driver on bcm6858. - -config NAND_BRCMNAND_63158 - bool "Support Broadcom NAND controller on bcm63158" - depends on NAND_BRCMNAND && BCM63158 - help - Enable support for broadcom nand driver on bcm63158. - config NAND_BRCMNAND_IPROC bool "Support Broadcom NAND controller on the iproc family" depends on NAND_BRCMNAND diff --git a/drivers/mtd/nand/raw/brcmnand/Makefile b/drivers/mtd/nand/raw/brcmnand/Makefile index 24d0d568449..4fba5c1c7e3 100644 --- a/drivers/mtd/nand/raw/brcmnand/Makefile +++ b/drivers/mtd/nand/raw/brcmnand/Makefile @@ -1,11 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_NAND_BRCMNAND_6368) += bcm6368_nand.o -obj-$(CONFIG_NAND_BRCMNAND_63158) += bcm63158_nand.o -obj-$(CONFIG_NAND_BRCMNAND_6753) += bcm6753_nand.o -obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o -obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o obj-$(CONFIG_NAND_BRCMNAND_BCMBCA) += bcmbca_nand.o obj-$(CONFIG_NAND_BRCMNAND_IPROC) += iproc_nand.o obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o diff --git a/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c deleted file mode 100644 index 3f59fbbbb8f..00000000000 --- a/drivers/mtd/nand/raw/brcmnand/bcm63158_nand.c +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "brcmnand.h" - -struct bcm63158_nand_soc { - struct brcmnand_soc soc; - void __iomem *base; -}; - -#define BCM63158_NAND_INT 0x00 -#define BCM63158_NAND_STATUS_SHIFT 0 -#define BCM63158_NAND_STATUS_MASK (0xfff << BCM63158_NAND_STATUS_SHIFT) - -#define BCM63158_NAND_INT_EN 0x04 -#define BCM63158_NAND_ENABLE_SHIFT 0 -#define BCM63158_NAND_ENABLE_MASK (0xffff << BCM63158_NAND_ENABLE_SHIFT) - -enum { - BCM63158_NP_READ = BIT(0), - BCM63158_BLOCK_ERASE = BIT(1), - BCM63158_COPY_BACK = BIT(2), - BCM63158_PAGE_PGM = BIT(3), - BCM63158_CTRL_READY = BIT(4), - BCM63158_DEV_RBPIN = BIT(5), - BCM63158_ECC_ERR_UNC = BIT(6), - BCM63158_ECC_ERR_CORR = BIT(7), -}; - -static bool bcm63158_nand_intc_ack(struct brcmnand_soc *soc) -{ - struct bcm63158_nand_soc *priv = - container_of(soc, struct bcm63158_nand_soc, soc); - void __iomem *mmio = priv->base + BCM63158_NAND_INT; - u32 val = brcmnand_readl(mmio); - - if (val & (BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT)) { - /* Ack interrupt */ - val &= ~BCM63158_NAND_STATUS_MASK; - val |= BCM63158_CTRL_READY << BCM63158_NAND_STATUS_SHIFT; - brcmnand_writel(val, mmio); - return true; - } - - return false; -} - -static void bcm63158_nand_intc_set(struct brcmnand_soc *soc, bool en) -{ - struct bcm63158_nand_soc *priv = - container_of(soc, struct bcm63158_nand_soc, soc); - void __iomem *mmio = priv->base + BCM63158_NAND_INT_EN; - u32 val = brcmnand_readl(mmio); - - /* Don't ack any interrupts */ - val &= ~BCM63158_NAND_STATUS_MASK; - - if (en) - val |= BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT; - else - val &= ~(BCM63158_CTRL_READY << BCM63158_NAND_ENABLE_SHIFT); - - brcmnand_writel(val, mmio); -} - -static int bcm63158_nand_probe(struct udevice *dev) -{ - struct udevice *pdev = dev; - struct bcm63158_nand_soc *priv = dev_get_priv(dev); - struct brcmnand_soc *soc; - struct resource res; - - soc = &priv->soc; - - dev_read_resource_byname(pdev, "nand-int-base", &res); - priv->base = devm_ioremap(dev, res.start, resource_size(&res)); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - - soc->ctlrdy_ack = bcm63158_nand_intc_ack; - soc->ctlrdy_set_enabled = bcm63158_nand_intc_set; - - /* Disable and ack all interrupts */ - brcmnand_writel(0, priv->base + BCM63158_NAND_INT_EN); - brcmnand_writel(0, priv->base + BCM63158_NAND_INT); - - return brcmnand_probe(pdev, soc); -} - -static const struct udevice_id bcm63158_nand_dt_ids[] = { - { - .compatible = "brcm,nand-bcm63158", - }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(bcm63158_nand) = { - .name = "bcm63158-nand", - .id = UCLASS_MTD, - .of_match = bcm63158_nand_dt_ids, - .probe = bcm63158_nand_probe, - .priv_auto = sizeof(struct bcm63158_nand_soc), -}; - -void board_nand_init(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MTD, - DM_DRIVER_GET(bcm63158_nand), &dev); - if (ret && ret != -ENODEV) - pr_err("Failed to initialize %s. (error %d)\n", dev->name, - ret); -} diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c deleted file mode 100644 index a101222a28f..00000000000 --- a/drivers/mtd/nand/raw/brcmnand/bcm6753_nand.c +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "brcmnand.h" - -struct bcm6753_nand_soc { - struct brcmnand_soc soc; - void __iomem *base; -}; - -#define BCM6753_NAND_INT 0x00 -#define BCM6753_NAND_STATUS_SHIFT 0 -#define BCM6753_NAND_STATUS_MASK (0xfff << BCM6753_NAND_STATUS_SHIFT) - -#define BCM6753_NAND_INT_EN 0x04 -#define BCM6753_NAND_ENABLE_SHIFT 0 -#define BCM6753_NAND_ENABLE_MASK (0xffff << BCM6753_NAND_ENABLE_SHIFT) - -enum { - BCM6753_NP_READ = BIT(0), - BCM6753_BLOCK_ERASE = BIT(1), - BCM6753_COPY_BACK = BIT(2), - BCM6753_PAGE_PGM = BIT(3), - BCM6753_CTRL_READY = BIT(4), - BCM6753_DEV_RBPIN = BIT(5), - BCM6753_ECC_ERR_UNC = BIT(6), - BCM6753_ECC_ERR_CORR = BIT(7), -}; - -static bool bcm6753_nand_intc_ack(struct brcmnand_soc *soc) -{ - struct bcm6753_nand_soc *priv = - container_of(soc, struct bcm6753_nand_soc, soc); - void __iomem *mmio = priv->base + BCM6753_NAND_INT; - u32 val = brcmnand_readl(mmio); - - if (val & (BCM6753_CTRL_READY << BCM6753_NAND_STATUS_SHIFT)) { - /* Ack interrupt */ - val &= ~BCM6753_NAND_STATUS_MASK; - val |= BCM6753_CTRL_READY << BCM6753_NAND_STATUS_SHIFT; - brcmnand_writel(val, mmio); - return true; - } - - return false; -} - -static void bcm6753_nand_intc_set(struct brcmnand_soc *soc, bool en) -{ - struct bcm6753_nand_soc *priv = - container_of(soc, struct bcm6753_nand_soc, soc); - void __iomem *mmio = priv->base + BCM6753_NAND_INT_EN; - u32 val = brcmnand_readl(mmio); - - /* Don't ack any interrupts */ - val &= ~BCM6753_NAND_STATUS_MASK; - - if (en) - val |= BCM6753_CTRL_READY << BCM6753_NAND_ENABLE_SHIFT; - else - val &= ~(BCM6753_CTRL_READY << BCM6753_NAND_ENABLE_SHIFT); - - brcmnand_writel(val, mmio); -} - -static int bcm6753_nand_probe(struct udevice *dev) -{ - struct udevice *pdev = dev; - struct bcm6753_nand_soc *priv = dev_get_priv(dev); - struct brcmnand_soc *soc; - struct resource res; - - soc = &priv->soc; - - dev_read_resource_byname(pdev, "nand-int-base", &res); - priv->base = devm_ioremap(dev, res.start, resource_size(&res)); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - - soc->ctlrdy_ack = bcm6753_nand_intc_ack; - soc->ctlrdy_set_enabled = bcm6753_nand_intc_set; - - /* Disable and ack all interrupts */ - brcmnand_writel(0, priv->base + BCM6753_NAND_INT_EN); - brcmnand_writel(0, priv->base + BCM6753_NAND_INT); - - return brcmnand_probe(pdev, soc); -} - -static const struct udevice_id bcm6753_nand_dt_ids[] = { - { - .compatible = "brcm,nand-bcm6753", - }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(bcm6753_nand) = { - .name = "bcm6753-nand", - .id = UCLASS_MTD, - .of_match = bcm6753_nand_dt_ids, - .probe = bcm6753_nand_probe, - .priv_auto = sizeof(struct bcm6753_nand_soc), -}; - -void board_nand_init(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MTD, - DM_DRIVER_GET(bcm6753_nand), &dev); - if (ret && ret != -ENODEV) - pr_err("Failed to initialize %s. (error %d)\n", dev->name, - ret); -} diff --git a/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c deleted file mode 100644 index 385642d0c09..00000000000 --- a/drivers/mtd/nand/raw/brcmnand/bcm68360_nand.c +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "brcmnand.h" - -struct bcm68360_nand_soc { - struct brcmnand_soc soc; - void __iomem *base; -}; - -#define BCM68360_NAND_INT 0x00 -#define BCM68360_NAND_STATUS_SHIFT 0 -#define BCM68360_NAND_STATUS_MASK (0xfff << BCM68360_NAND_STATUS_SHIFT) - -#define BCM68360_NAND_INT_EN 0x04 -#define BCM68360_NAND_ENABLE_SHIFT 0 -#define BCM68360_NAND_ENABLE_MASK (0xffff << BCM68360_NAND_ENABLE_SHIFT) - -enum { - BCM68360_NP_READ = BIT(0), - BCM68360_BLOCK_ERASE = BIT(1), - BCM68360_COPY_BACK = BIT(2), - BCM68360_PAGE_PGM = BIT(3), - BCM68360_CTRL_READY = BIT(4), - BCM68360_DEV_RBPIN = BIT(5), - BCM68360_ECC_ERR_UNC = BIT(6), - BCM68360_ECC_ERR_CORR = BIT(7), -}; - -static bool bcm68360_nand_intc_ack(struct brcmnand_soc *soc) -{ - struct bcm68360_nand_soc *priv = - container_of(soc, struct bcm68360_nand_soc, soc); - void __iomem *mmio = priv->base + BCM68360_NAND_INT; - u32 val = brcmnand_readl(mmio); - - if (val & (BCM68360_CTRL_READY << BCM68360_NAND_STATUS_SHIFT)) { - /* Ack interrupt */ - val &= ~BCM68360_NAND_STATUS_MASK; - val |= BCM68360_CTRL_READY << BCM68360_NAND_STATUS_SHIFT; - brcmnand_writel(val, mmio); - return true; - } - - return false; -} - -static void bcm68360_nand_intc_set(struct brcmnand_soc *soc, bool en) -{ - struct bcm68360_nand_soc *priv = - container_of(soc, struct bcm68360_nand_soc, soc); - void __iomem *mmio = priv->base + BCM68360_NAND_INT_EN; - u32 val = brcmnand_readl(mmio); - - /* Don't ack any interrupts */ - val &= ~BCM68360_NAND_STATUS_MASK; - - if (en) - val |= BCM68360_CTRL_READY << BCM68360_NAND_ENABLE_SHIFT; - else - val &= ~(BCM68360_CTRL_READY << BCM68360_NAND_ENABLE_SHIFT); - - brcmnand_writel(val, mmio); -} - -static int bcm68360_nand_probe(struct udevice *dev) -{ - struct udevice *pdev = dev; - struct bcm68360_nand_soc *priv = dev_get_priv(dev); - struct brcmnand_soc *soc; - struct resource res; - - soc = &priv->soc; - - dev_read_resource_byname(pdev, "nand-int-base", &res); - priv->base = devm_ioremap(dev, res.start, resource_size(&res)); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - - soc->ctlrdy_ack = bcm68360_nand_intc_ack; - soc->ctlrdy_set_enabled = bcm68360_nand_intc_set; - - /* Disable and ack all interrupts */ - brcmnand_writel(0, priv->base + BCM68360_NAND_INT_EN); - brcmnand_writel(0, priv->base + BCM68360_NAND_INT); - - return brcmnand_probe(pdev, soc); -} - -static const struct udevice_id bcm68360_nand_dt_ids[] = { - { - .compatible = "brcm,nand-bcm68360", - }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(bcm68360_nand) = { - .name = "bcm68360-nand", - .id = UCLASS_MTD, - .of_match = bcm68360_nand_dt_ids, - .probe = bcm68360_nand_probe, - .priv_auto = sizeof(struct bcm68360_nand_soc), -}; - -void board_nand_init(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MTD, - DM_DRIVER_GET(bcm68360_nand), &dev); - if (ret && ret != -ENODEV) - pr_err("Failed to initialize %s. (error %d)\n", dev->name, - ret); -} diff --git a/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c deleted file mode 100644 index 564c678c9ef..00000000000 --- a/drivers/mtd/nand/raw/brcmnand/bcm6858_nand.c +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "brcmnand.h" - -struct bcm6858_nand_soc { - struct brcmnand_soc soc; - void __iomem *base; -}; - -#define BCM6858_NAND_INT 0x00 -#define BCM6858_NAND_STATUS_SHIFT 0 -#define BCM6858_NAND_STATUS_MASK (0xfff << BCM6858_NAND_STATUS_SHIFT) - -#define BCM6858_NAND_INT_EN 0x04 -#define BCM6858_NAND_ENABLE_SHIFT 0 -#define BCM6858_NAND_ENABLE_MASK (0xffff << BCM6858_NAND_ENABLE_SHIFT) - -enum { - BCM6858_NP_READ = BIT(0), - BCM6858_BLOCK_ERASE = BIT(1), - BCM6858_COPY_BACK = BIT(2), - BCM6858_PAGE_PGM = BIT(3), - BCM6858_CTRL_READY = BIT(4), - BCM6858_DEV_RBPIN = BIT(5), - BCM6858_ECC_ERR_UNC = BIT(6), - BCM6858_ECC_ERR_CORR = BIT(7), -}; - -static bool bcm6858_nand_intc_ack(struct brcmnand_soc *soc) -{ - struct bcm6858_nand_soc *priv = - container_of(soc, struct bcm6858_nand_soc, soc); - void __iomem *mmio = priv->base + BCM6858_NAND_INT; - u32 val = brcmnand_readl(mmio); - - if (val & (BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT)) { - /* Ack interrupt */ - val &= ~BCM6858_NAND_STATUS_MASK; - val |= BCM6858_CTRL_READY << BCM6858_NAND_STATUS_SHIFT; - brcmnand_writel(val, mmio); - return true; - } - - return false; -} - -static void bcm6858_nand_intc_set(struct brcmnand_soc *soc, bool en) -{ - struct bcm6858_nand_soc *priv = - container_of(soc, struct bcm6858_nand_soc, soc); - void __iomem *mmio = priv->base + BCM6858_NAND_INT_EN; - u32 val = brcmnand_readl(mmio); - - /* Don't ack any interrupts */ - val &= ~BCM6858_NAND_STATUS_MASK; - - if (en) - val |= BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT; - else - val &= ~(BCM6858_CTRL_READY << BCM6858_NAND_ENABLE_SHIFT); - - brcmnand_writel(val, mmio); -} - -static int bcm6858_nand_probe(struct udevice *dev) -{ - struct udevice *pdev = dev; - struct bcm6858_nand_soc *priv = dev_get_priv(dev); - struct brcmnand_soc *soc; - struct resource res; - - soc = &priv->soc; - - dev_read_resource_byname(pdev, "nand-int-base", &res); - priv->base = devm_ioremap(dev, res.start, resource_size(&res)); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - - soc->ctlrdy_ack = bcm6858_nand_intc_ack; - soc->ctlrdy_set_enabled = bcm6858_nand_intc_set; - - /* Disable and ack all interrupts */ - brcmnand_writel(0, priv->base + BCM6858_NAND_INT_EN); - brcmnand_writel(0, priv->base + BCM6858_NAND_INT); - - return brcmnand_probe(pdev, soc); -} - -static const struct udevice_id bcm6858_nand_dt_ids[] = { - { - .compatible = "brcm,nand-bcm6858", - }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(bcm6858_nand) = { - .name = "bcm6858-nand", - .id = UCLASS_MTD, - .of_match = bcm6858_nand_dt_ids, - .probe = bcm6858_nand_probe, - .priv_auto = sizeof(struct bcm6858_nand_soc), -}; - -void board_nand_init(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MTD, - DM_DRIVER_GET(bcm6858_nand), &dev); - if (ret && ret != -ENODEV) - pr_err("Failed to initialize %s. (error %d)\n", dev->name, - ret); -} From 67e52b59a2faba4ea44f63bcdc3fffc43209a15d Mon Sep 17 00:00:00 2001 From: david regan Date: Tue, 12 Nov 2024 22:27:13 -0800 Subject: [PATCH 17/57] arm: dts: Use upstream dts Make use of OF_UPSTREAM which uses Linux dts. Signed-off-by: david regan Reviewed-by: Linus Walleij Reviewed-by: Sumit Garg Reviewed-by: William Zhang Reviewed-by: Anand Gore --- arch/arm/dts/bcm47622.dtsi | 126 ------------ arch/arm/dts/bcm4912.dtsi | 128 ------------ arch/arm/dts/bcm63146.dtsi | 110 ---------- arch/arm/dts/bcm63158.dtsi | 278 -------------------------- arch/arm/dts/bcm63178.dtsi | 120 ----------- arch/arm/dts/bcm6756.dtsi | 130 ------------ arch/arm/dts/bcm6813.dtsi | 128 ------------ arch/arm/dts/bcm6855.dtsi | 257 ------------------------ arch/arm/dts/bcm6856.dtsi | 253 ----------------------- arch/arm/dts/bcm6858.dtsi | 272 ------------------------- arch/arm/dts/bcm6878.dtsi | 111 ---------- arch/arm/dts/bcm947622.dts | 30 --- arch/arm/dts/bcm94912.dts | 30 --- arch/arm/dts/bcm963146.dts | 30 --- arch/arm/dts/bcm963158.dts | 30 --- arch/arm/dts/bcm963178.dts | 30 --- arch/arm/dts/bcm96756.dts | 30 --- arch/arm/dts/bcm96813.dts | 30 --- arch/arm/dts/bcm96855.dts | 30 --- arch/arm/dts/bcm96856.dts | 30 --- arch/arm/dts/bcm96858.dts | 30 --- arch/arm/dts/bcm96878.dts | 30 --- arch/arm/mach-bcmbca/bcm47622/Kconfig | 1 + arch/arm/mach-bcmbca/bcm4912/Kconfig | 1 + arch/arm/mach-bcmbca/bcm63146/Kconfig | 1 + arch/arm/mach-bcmbca/bcm63158/Kconfig | 1 + arch/arm/mach-bcmbca/bcm63178/Kconfig | 1 + arch/arm/mach-bcmbca/bcm6756/Kconfig | 1 + arch/arm/mach-bcmbca/bcm6813/Kconfig | 1 + arch/arm/mach-bcmbca/bcm6855/Kconfig | 1 + arch/arm/mach-bcmbca/bcm6856/Kconfig | 1 + arch/arm/mach-bcmbca/bcm6858/Kconfig | 1 + arch/arm/mach-bcmbca/bcm6878/Kconfig | 1 + configs/bcm947622_defconfig | 11 +- configs/bcm94912_defconfig | 11 +- configs/bcm963146_defconfig | 11 +- configs/bcm963158_defconfig | 11 +- configs/bcm963178_defconfig | 11 +- configs/bcm96756_defconfig | 11 +- configs/bcm96813_defconfig | 11 +- configs/bcm96855_defconfig | 11 +- configs/bcm96856_defconfig | 11 +- configs/bcm96858_defconfig | 11 +- configs/bcm96878_defconfig | 11 +- 44 files changed, 121 insertions(+), 2254 deletions(-) delete mode 100644 arch/arm/dts/bcm47622.dtsi delete mode 100644 arch/arm/dts/bcm4912.dtsi delete mode 100644 arch/arm/dts/bcm63146.dtsi delete mode 100644 arch/arm/dts/bcm63158.dtsi delete mode 100644 arch/arm/dts/bcm63178.dtsi delete mode 100644 arch/arm/dts/bcm6756.dtsi delete mode 100644 arch/arm/dts/bcm6813.dtsi delete mode 100644 arch/arm/dts/bcm6855.dtsi delete mode 100644 arch/arm/dts/bcm6856.dtsi delete mode 100644 arch/arm/dts/bcm6858.dtsi delete mode 100644 arch/arm/dts/bcm6878.dtsi delete mode 100644 arch/arm/dts/bcm947622.dts delete mode 100644 arch/arm/dts/bcm94912.dts delete mode 100644 arch/arm/dts/bcm963146.dts delete mode 100644 arch/arm/dts/bcm963158.dts delete mode 100644 arch/arm/dts/bcm963178.dts delete mode 100644 arch/arm/dts/bcm96756.dts delete mode 100644 arch/arm/dts/bcm96813.dts delete mode 100644 arch/arm/dts/bcm96855.dts delete mode 100644 arch/arm/dts/bcm96856.dts delete mode 100644 arch/arm/dts/bcm96858.dts delete mode 100644 arch/arm/dts/bcm96878.dts diff --git a/arch/arm/dts/bcm47622.dtsi b/arch/arm/dts/bcm47622.dtsi deleted file mode 100644 index c016e12b737..00000000000 --- a/arch/arm/dts/bcm47622.dtsi +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm47622", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - CA7_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - CA7_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&CA7_0>, <&CA7_1>, - <&CA7_2>, <&CA7_3>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - cpu_off = <1>; - cpu_on = <2>; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x818000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1000 0x1000>, - <0x2000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = ; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm4912.dtsi b/arch/arm/dts/bcm4912.dtsi deleted file mode 100644 index 3d016c2ce67..00000000000 --- a/arch/arm/dts/bcm4912.dtsi +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm4912", "brcm,bcmbca"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - B53_0: cpu@0 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_1: cpu@1 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_2: cpu@2 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_3: cpu@3 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&B53_0>, <&B53_1>, - <&B53_2>, <&B53_3>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = ; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm63146.dtsi b/arch/arm/dts/bcm63146.dtsi deleted file mode 100644 index 04de96bd0a0..00000000000 --- a/arch/arm/dts/bcm63146.dtsi +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm63146", "brcm,bcmbca"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - B53_0: cpu@0 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_1: cpu@1 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - ; - interrupt-affinity = <&B53_0>, <&B53_1>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - interrupts = ; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = ; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi deleted file mode 100644 index 4bed1f914a9..00000000000 --- a/arch/arm/dts/bcm63158.dtsi +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019 Philippe Reynes - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm63158", "brcm,bcmbca"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - B53_0: cpu@0 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_1: cpu@1 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_2: cpu@2 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_3: cpu@3 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&B53_0>, <&B53_1>, - <&B53_2>, <&B53_3>; - }; - - clocks { - bootph-all; - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-mult = <2>; - clock-div = <1>; - }; - - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - - wdt_clk: wdt-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - bootph-all; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = ; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - - leds: led-controller@800 { - compatible = "brcm,bcm6858-leds"; - reg = <0x800 0xe4>; - - status = "disabled"; - }; - - wdt1: watchdog@480 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x480 0x14>; - clocks = <&wdt_clk>; - }; - - wdt2: watchdog@4c0 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x4c0 0x14>; - clocks = <&wdt_clk>; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdt1>; - }; - - gpio0: gpio-controller@500 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x500 0x4>, - <0x520 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio1: gpio-controller@504 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x504 0x4>, - <0x524 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio2: gpio-controller@508 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x508 0x4>, - <0x528 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio3: gpio-controller@50c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x50c 0x4>, - <0x52c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio4: gpio-controller@510 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x510 0x4>, - <0x530 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio5: gpio-controller@514 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x514 0x4>, - <0x534 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio6: gpio-controller@518 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x518 0x4>, - <0x538 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio7: gpio-controller@51c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x51c 0x4>, - <0x53c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - hsspi: spi-controller@1000 { - compatible = "brcm,bcm6328-hsspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1000 0x600>; - clocks = <&hsspi_pll>, <&hsspi_pll>; - clock-names = "hsspi", "pll"; - spi-max-frequency = <100000000>; - num-cs = <8>; - - status = "disabled"; - }; - - nand: nand-controller@1800 { - compatible = "brcm,nand-bcm63158", - "brcm,brcmnand-v5.0", - "brcm,brcmnand"; - reg-names = "nand", "nand-int-base", "nand-cache"; - reg = <0x1800 0x180>, - <0x2000 0x10>, - <0x1c00 0x200>; - parameter-page-big-endian = <0>; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm63178.dtsi b/arch/arm/dts/bcm63178.dtsi deleted file mode 100644 index cbd094dde6d..00000000000 --- a/arch/arm/dts/bcm63178.dtsi +++ /dev/null @@ -1,120 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm63178", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - ; - interrupt-affinity = <&CA7_0>, <&CA7_1>, - <&CA7_2>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = ; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm6756.dtsi b/arch/arm/dts/bcm6756.dtsi deleted file mode 100644 index ce1b59faf80..00000000000 --- a/arch/arm/dts/bcm6756.dtsi +++ /dev/null @@ -1,130 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm6756", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&CA7_0>, <&CA7_1>, - <&CA7_2>, <&CA7_3>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = ; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm6813.dtsi b/arch/arm/dts/bcm6813.dtsi deleted file mode 100644 index c3e6197be80..00000000000 --- a/arch/arm/dts/bcm6813.dtsi +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm6813", "brcm,bcmbca"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - B53_0: cpu@0 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_1: cpu@1 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_2: cpu@2 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_3: cpu@3 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&B53_0>, <&B53_1>, - <&B53_2>, <&B53_3>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = ; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm6855.dtsi b/arch/arm/dts/bcm6855.dtsi deleted file mode 100644 index 10c003a57c9..00000000000 --- a/arch/arm/dts/bcm6855.dtsi +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2022 Philippe Reynes - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm6855", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - ; - interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>; - }; - - clocks: clocks { - bootph-all; - - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-mult = <2>; - clock-div = <1>; - }; - - wdt_clk: wdt-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - bootph-all; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = ; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - - wdt1: watchdog@480 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x480 0x14>; - clocks = <&wdt_clk>; - }; - - wdt2: watchdog@4c0 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x4c0 0x14>; - clocks = <&wdt_clk>; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdt1>; - }; - - gpio0: gpio-controller@500 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x500 0x4>, - <0x520 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio1: gpio-controller@504 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x504 0x4>, - <0x524 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio2: gpio-controller@508 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x508 0x4>, - <0x528 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio3: gpio-controller@50c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x50c 0x4>, - <0x52c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio4: gpio-controller@510 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x510 0x4>, - <0x530 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio5: gpio-controller@514 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x514 0x4>, - <0x534 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio6: gpio-controller@518 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x518 0x4>, - <0x538 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio7: gpio-controller@51c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x51c 0x4>, - <0x53c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - nand: nand-controller@1800 { - compatible = "brcm,nand-bcm6753", - "brcm,brcmnand-v5.0", - "brcm,brcmnand"; - reg-names = "nand", "nand-int-base", "nand-cache"; - reg = <0x1800 0x180>, - <0x2000 0x10>, - <0x1c00 0x200>; - parameter-page-big-endian = <0>; - - status = "disabled"; - }; - - leds: led-controller@3000 { - compatible = "brcm,bcm6753-leds"; - reg = <0x3000 0x3480>; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm6856.dtsi b/arch/arm/dts/bcm6856.dtsi deleted file mode 100644 index 38c88f8399b..00000000000 --- a/arch/arm/dts/bcm6856.dtsi +++ /dev/null @@ -1,253 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Philippe Reynes - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm6856", "brcm,bcmbca"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - B53_0: cpu@0 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_1: cpu@1 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - ; - interrupt-affinity = <&B53_0>, <&B53_1>; - }; - - clocks: clocks { - bootph-all; - - periph_clk:periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-mult = <2>; - clock-div = <1>; - }; - - wdt_clk: wdt-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x1000 0x1000>, /* GICD */ - <0x2000 0x2000>, /* GICC */ - <0x4000 0x2000>, /* GICH */ - <0x6000 0x2000>; /* GICV */ - interrupts = ; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - bootph-all; - - uart0: serial@640 { - compatible = "brcm,bcm6345-uart"; - reg = <0x640 0x18>; - interrupts = ; - clocks = <&periph_clk>; - clock-names = "refclk"; - status = "disabled"; - }; - - wdt1: watchdog@480 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x480 0x14>; - clocks = <&wdt_clk>; - }; - - wdt2: watchdog@4c0 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x4c0 0x14>; - clocks = <&wdt_clk>; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdt1>; - }; - - leds: led-controller@800 { - compatible = "brcm,bcm6858-leds"; - reg = <0x800 0xe4>; - - status = "disabled"; - }; - - gpio0: gpio-controller@500 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x500 0x4>, - <0x520 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio1: gpio-controller@504 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x504 0x4>, - <0x524 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio2: gpio-controller@508 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x508 0x4>, - <0x528 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio3: gpio-controller@50c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x50c 0x4>, - <0x52c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio4: gpio-controller@510 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x510 0x4>, - <0x530 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio5: gpio-controller@514 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x514 0x4>, - <0x534 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio6: gpio-controller@518 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x518 0x4>, - <0x538 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio7: gpio-controller@51c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x51c 0x4>, - <0x53c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - hsspi: spi-controller@1000 { - compatible = "brcm,bcm6328-hsspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1000 0x600>; - clocks = <&hsspi_pll>, <&hsspi_pll>; - clock-names = "hsspi", "pll"; - spi-max-frequency = <100000000>; - num-cs = <8>; - - status = "disabled"; - }; - - nand: nand-controller@1800 { - compatible = "brcm,nand-bcm68360", - "brcm,brcmnand-v5.0", - "brcm,brcmnand"; - reg-names = "nand", "nand-int-base", "nand-cache"; - reg = <0x1800 0x180>, - <0x2000 0x10>, - <0x1c00 0x200>; - parameter-page-big-endian = <0>; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi deleted file mode 100644 index dc95047a265..00000000000 --- a/arch/arm/dts/bcm6858.dtsi +++ /dev/null @@ -1,272 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Philippe Reynes - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm6858", "brcm,bcmbca"; - #address-cells = <2>; - #size-cells = <2>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - B53_0: cpu@0 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_1: cpu@1 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_2: cpu@2 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x2>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - B53_3: cpu@3 { - compatible = "brcm,brahma-b53"; - device_type = "cpu"; - reg = <0x0 0x3>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu: pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - interrupt-affinity = <&B53_0>, <&B53_1>, - <&B53_2>, <&B53_3>; - }; - - clocks { - bootph-all; - - periph_clk: periph_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-mult = <2>; - clock-div = <1>; - }; - - wdt_clk: wdt-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x1000 0x1000>, /* GICD */ - <0x2000 0x2000>, /* GICC */ - <0x4000 0x2000>, /* GICH */ - <0x6000 0x2000>; /* GICV */ - interrupts = ; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0xff800000 0x800000>; - bootph-all; - - uart0: serial@640 { - compatible = "brcm,bcm6345-uart"; - reg = <0x640 0x18>; - interrupts = ; - clocks = <&periph_clk>; - clock-names = "refclk"; - status = "disabled"; - }; - - leds: led-controller@800 { - compatible = "brcm,bcm6858-leds"; - reg = <0x800 0xe4>; - - status = "disabled"; - }; - - wdt1: watchdog@2780 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x2780 0x14>; - clocks = <&wdt_clk>; - }; - - wdt2: watchdog@27c0 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x27c0 0x14>; - clocks = <&wdt_clk>; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdt1>; - }; - - gpio0: gpio-controller@500 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x500 0x4>, - <0x520 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio1: gpio-controller@504 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x504 0x4>, - <0x524 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio2: gpio-controller@508 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x508 0x4>, - <0x528 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio3: gpio-controller@50c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x50c 0x4>, - <0x52c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio4: gpio-controller@510 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x510 0x4>, - <0x530 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio5: gpio-controller@514 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x514 0x4>, - <0x534 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio6: gpio-controller@518 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x518 0x4>, - <0x538 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio7: gpio-controller@51c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x51c 0x4>, - <0x53c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - hsspi: spi-controller@1000 { - compatible = "brcm,bcm6328-hsspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1000 0x600>; - clocks = <&hsspi_pll>, <&hsspi_pll>; - clock-names = "hsspi", "pll"; - spi-max-frequency = <100000000>; - num-cs = <8>; - - status = "disabled"; - }; - - nand: nand-controller@1800 { - compatible = "brcm,nand-bcm6858", - "brcm,brcmnand-v5.0", - "brcm,brcmnand"; - reg-names = "nand", "nand-int-base", "nand-cache"; - reg = <0x1800 0x180>, - <0x2000 0x10>, - <0x1c00 0x200>; - parameter-page-big-endian = <0>; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm6878.dtsi b/arch/arm/dts/bcm6878.dtsi deleted file mode 100644 index 1e8b5fa96c2..00000000000 --- a/arch/arm/dts/bcm6878.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -#include -#include - -/ { - compatible = "brcm,bcm6878", "brcm,bcmbca"; - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - CA7_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CA7_1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0x1>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - L2_0: l2-cache0 { - compatible = "cache"; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - arm,cpu-registers-not-fw-configured; - }; - - pmu: pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - ; - interrupt-affinity = <&CA7_0>, <&CA7_1>; - }; - - clocks: clocks { - periph_clk: periph-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - uart_clk: uart-clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_clk>; - clock-div = <4>; - clock-mult = <1>; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - axi@81000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x81000000 0x8000>; - - gic: interrupt-controller@1000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x1000 0x1000>, - <0x2000 0x2000>, - <0x4000 0x2000>, - <0x6000 0x2000>; - interrupts = ; - }; - }; - - bus@ff800000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xff800000 0x800000>; - - uart0: serial@12000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x12000 0x1000>; - interrupts = ; - clocks = <&uart_clk>, <&uart_clk>; - clock-names = "uartclk", "apb_pclk"; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm947622.dts b/arch/arm/dts/bcm947622.dts deleted file mode 100644 index 6f083724ab8..00000000000 --- a/arch/arm/dts/bcm947622.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm47622.dtsi" - -/ { - model = "Broadcom BCM947622 Reference Board"; - compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm94912.dts b/arch/arm/dts/bcm94912.dts deleted file mode 100644 index a3623e6f691..00000000000 --- a/arch/arm/dts/bcm94912.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm4912.dtsi" - -/ { - model = "Broadcom BCM94912 Reference Board"; - compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm963146.dts b/arch/arm/dts/bcm963146.dts deleted file mode 100644 index e39f1e6d477..00000000000 --- a/arch/arm/dts/bcm963146.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm63146.dtsi" - -/ { - model = "Broadcom BCM963146 Reference Board"; - compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts deleted file mode 100644 index eba07e0b1ca..00000000000 --- a/arch/arm/dts/bcm963158.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm63158.dtsi" - -/ { - model = "Broadcom BCM963158 Reference Board"; - compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm963178.dts b/arch/arm/dts/bcm963178.dts deleted file mode 100644 index fa096e9cde2..00000000000 --- a/arch/arm/dts/bcm963178.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm63178.dtsi" - -/ { - model = "Broadcom BCM963178 Reference Board"; - compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm96756.dts b/arch/arm/dts/bcm96756.dts deleted file mode 100644 index 9a4a87ba9c8..00000000000 --- a/arch/arm/dts/bcm96756.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6756.dtsi" - -/ { - model = "Broadcom BCM96756 Reference Board"; - compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm96813.dts b/arch/arm/dts/bcm96813.dts deleted file mode 100644 index af17091ae76..00000000000 --- a/arch/arm/dts/bcm96813.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6813.dtsi" - -/ { - model = "Broadcom BCM96813 Reference Board"; - compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm96855.dts b/arch/arm/dts/bcm96855.dts deleted file mode 100644 index e4e740c73e9..00000000000 --- a/arch/arm/dts/bcm96855.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6855.dtsi" - -/ { - model = "Broadcom BCM96855 Reference Board"; - compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm96856.dts b/arch/arm/dts/bcm96856.dts deleted file mode 100644 index 032aeb75c98..00000000000 --- a/arch/arm/dts/bcm96856.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6856.dtsi" - -/ { - model = "Broadcom BCM96856 Reference Board"; - compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm96858.dts b/arch/arm/dts/bcm96858.dts deleted file mode 100644 index 0cbf582f5d5..00000000000 --- a/arch/arm/dts/bcm96858.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6858.dtsi" - -/ { - model = "Broadcom BCM96858 Reference Board"; - compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/bcm96878.dts b/arch/arm/dts/bcm96878.dts deleted file mode 100644 index 8fbc175cb45..00000000000 --- a/arch/arm/dts/bcm96878.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2019 Broadcom Ltd. - */ - -/dts-v1/; - -#include "bcm6878.dtsi" - -/ { - model = "Broadcom BCM96878 Reference Board"; - compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x08000000>; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/arm/mach-bcmbca/bcm47622/Kconfig b/arch/arm/mach-bcmbca/bcm47622/Kconfig index bce30892e35..56ce280a1cd 100644 --- a/arch/arm/mach-bcmbca/bcm47622/Kconfig +++ b/arch/arm/mach-bcmbca/bcm47622/Kconfig @@ -8,6 +8,7 @@ if BCM47622 config TARGET_BCM947622 bool "Broadcom 47622 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm47622" diff --git a/arch/arm/mach-bcmbca/bcm4912/Kconfig b/arch/arm/mach-bcmbca/bcm4912/Kconfig index b8c14d1dc1a..9844ddeb8b8 100644 --- a/arch/arm/mach-bcmbca/bcm4912/Kconfig +++ b/arch/arm/mach-bcmbca/bcm4912/Kconfig @@ -8,6 +8,7 @@ if BCM4912 config TARGET_BCM94912 bool "Broadcom 4912 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm4912" diff --git a/arch/arm/mach-bcmbca/bcm63146/Kconfig b/arch/arm/mach-bcmbca/bcm63146/Kconfig index 690cbf1eb20..7c26742e474 100644 --- a/arch/arm/mach-bcmbca/bcm63146/Kconfig +++ b/arch/arm/mach-bcmbca/bcm63146/Kconfig @@ -8,6 +8,7 @@ if BCM63146 config TARGET_BCM963146 bool "Broadcom 63146 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm63146" diff --git a/arch/arm/mach-bcmbca/bcm63158/Kconfig b/arch/arm/mach-bcmbca/bcm63158/Kconfig index b77444369ec..6db7b36aa32 100644 --- a/arch/arm/mach-bcmbca/bcm63158/Kconfig +++ b/arch/arm/mach-bcmbca/bcm63158/Kconfig @@ -8,6 +8,7 @@ if BCM63158 config TARGET_BCM963158 bool "Broadcom 63158 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm63158" diff --git a/arch/arm/mach-bcmbca/bcm63178/Kconfig b/arch/arm/mach-bcmbca/bcm63178/Kconfig index 73ac46284b2..167acfff2c9 100644 --- a/arch/arm/mach-bcmbca/bcm63178/Kconfig +++ b/arch/arm/mach-bcmbca/bcm63178/Kconfig @@ -8,6 +8,7 @@ if BCM63178 config TARGET_BCM963178 bool "Broadcom 63178 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm63178" diff --git a/arch/arm/mach-bcmbca/bcm6756/Kconfig b/arch/arm/mach-bcmbca/bcm6756/Kconfig index c83dcd0f3e2..bbaa45eaab0 100644 --- a/arch/arm/mach-bcmbca/bcm6756/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6756/Kconfig @@ -8,6 +8,7 @@ if BCM6756 config TARGET_BCM96756 bool "Broadcom 6756 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm6756" diff --git a/arch/arm/mach-bcmbca/bcm6813/Kconfig b/arch/arm/mach-bcmbca/bcm6813/Kconfig index 25a4221bef9..0cda69cb43e 100644 --- a/arch/arm/mach-bcmbca/bcm6813/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6813/Kconfig @@ -8,6 +8,7 @@ if BCM6813 config TARGET_BCM96813 bool "Broadcom 6813 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm6813" diff --git a/arch/arm/mach-bcmbca/bcm6855/Kconfig b/arch/arm/mach-bcmbca/bcm6855/Kconfig index 78087c7dd59..31eaaed7ca2 100644 --- a/arch/arm/mach-bcmbca/bcm6855/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6855/Kconfig @@ -8,6 +8,7 @@ if BCM6855 config TARGET_BCM96855 bool "Broadcom 6855 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm6855" diff --git a/arch/arm/mach-bcmbca/bcm6856/Kconfig b/arch/arm/mach-bcmbca/bcm6856/Kconfig index 6ac75cb8409..7b09a1577bb 100644 --- a/arch/arm/mach-bcmbca/bcm6856/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6856/Kconfig @@ -8,6 +8,7 @@ if BCM6856 config TARGET_BCM96856 bool "Broadcom 6856 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm6856" diff --git a/arch/arm/mach-bcmbca/bcm6858/Kconfig b/arch/arm/mach-bcmbca/bcm6858/Kconfig index a6504bae1f1..d32107a17a8 100644 --- a/arch/arm/mach-bcmbca/bcm6858/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6858/Kconfig @@ -8,6 +8,7 @@ if BCM6858 config TARGET_BCM96858 bool "Broadcom 6858 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm6858" diff --git a/arch/arm/mach-bcmbca/bcm6878/Kconfig b/arch/arm/mach-bcmbca/bcm6878/Kconfig index 43f8942c9b1..2365cfde6ec 100644 --- a/arch/arm/mach-bcmbca/bcm6878/Kconfig +++ b/arch/arm/mach-bcmbca/bcm6878/Kconfig @@ -8,6 +8,7 @@ if BCM6878 config TARGET_BCM96878 bool "Broadcom 6878 Reference Board" depends on ARCH_BCMBCA + imply OF_UPSTREAM config SYS_SOC default "bcm6878" diff --git a/configs/bcm947622_defconfig b/configs/bcm947622_defconfig index 71057f1dc04..cf0651c6502 100644 --- a/configs/bcm947622_defconfig +++ b/configs/bcm947622_defconfig @@ -8,7 +8,7 @@ CONFIG_TARGET_BCM947622=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm947622" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm947622" CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM47622" @@ -16,6 +16,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y +CONFIG_DM=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm94912_defconfig b/configs/bcm94912_defconfig index 5b6de30cd8b..bce823b9041 100644 --- a/configs/bcm94912_defconfig +++ b/configs/bcm94912_defconfig @@ -9,13 +9,22 @@ CONFIG_TARGET_BCM94912=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm94912" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm94912" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM4912" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y +CONFIG_DM=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm963146_defconfig b/configs/bcm963146_defconfig index 5033b069d7d..691d055e310 100644 --- a/configs/bcm963146_defconfig +++ b/configs/bcm963146_defconfig @@ -9,13 +9,22 @@ CONFIG_TARGET_BCM963146=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm963146" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm963146" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM63146" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y +CONFIG_DM=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm963158_defconfig b/configs/bcm963158_defconfig index c3010d97908..6e4a85ec3a3 100644 --- a/configs/bcm963158_defconfig +++ b/configs/bcm963158_defconfig @@ -9,13 +9,22 @@ CONFIG_TARGET_BCM963158=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm963158" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm963158" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM63158" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y +CONFIG_DM=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm963178_defconfig b/configs/bcm963178_defconfig index 1409febae14..60a198719a3 100644 --- a/configs/bcm963178_defconfig +++ b/configs/bcm963178_defconfig @@ -9,7 +9,7 @@ CONFIG_TARGET_BCM963178=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm963178" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm963178" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM63178" @@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y +CONFIG_DM=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm96756_defconfig b/configs/bcm96756_defconfig index 96a9a311037..4b1fa991a04 100644 --- a/configs/bcm96756_defconfig +++ b/configs/bcm96756_defconfig @@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96756=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm96756" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96756" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM6756" @@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y +CONFIG_DM=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm96813_defconfig b/configs/bcm96813_defconfig index eadcb6374c6..553bdc148b2 100644 --- a/configs/bcm96813_defconfig +++ b/configs/bcm96813_defconfig @@ -9,13 +9,22 @@ CONFIG_TARGET_BCM96813=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm96813" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96813" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM6813" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y +CONFIG_DM=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm96855_defconfig b/configs/bcm96855_defconfig index 6ffae45faa2..ff6dff0fca6 100644 --- a/configs/bcm96855_defconfig +++ b/configs/bcm96855_defconfig @@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96855=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm96855" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96855" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM6855" @@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y +CONFIG_DM=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm96856_defconfig b/configs/bcm96856_defconfig index f926b3770f0..7c6fba29abf 100644 --- a/configs/bcm96856_defconfig +++ b/configs/bcm96856_defconfig @@ -9,13 +9,22 @@ CONFIG_TARGET_BCM96856=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm96856" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96856" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM6856" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y +CONFIG_DM=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm96858_defconfig b/configs/bcm96858_defconfig index cc6069fe794..3e11b401260 100644 --- a/configs/bcm96858_defconfig +++ b/configs/bcm96858_defconfig @@ -9,13 +9,22 @@ CONFIG_TARGET_BCM96858=y CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm96858" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcmbca/bcm96858" CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM6858" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y +CONFIG_DM=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y diff --git a/configs/bcm96878_defconfig b/configs/bcm96878_defconfig index 7d1cd6c944f..52c869aab9b 100644 --- a/configs/bcm96878_defconfig +++ b/configs/bcm96878_defconfig @@ -9,7 +9,7 @@ CONFIG_TARGET_BCM96878=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000 -CONFIG_DEFAULT_DEVICE_TREE="bcm96878" +CONFIG_DEFAULT_DEVICE_TREE="broadcom/bcm96878" CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x01000000 CONFIG_IDENT_STRING=" Broadcom BCM6878" @@ -17,6 +17,15 @@ CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y +CONFIG_DM=y CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BRCMNAND=y +CONFIG_NAND_BRCMNAND_BCMBCA=y From a4f72e8b6ef25530e7fe6a8b25920126f2a5d81f Mon Sep 17 00:00:00 2001 From: david regan Date: Tue, 12 Nov 2024 22:27:14 -0800 Subject: [PATCH 18/57] mtd: rawnand: brcmnand: Default bcmbca parameter_page_big_endian to zero Set parameter_page_big_endian to zero for bcmbca Signed-off-by: david regan Reviewed-by: William Zhang Reviewed-by: Anand Gore --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 749553c9df9..7fd9e1855d1 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -2793,9 +2793,17 @@ int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc) nand_hw_control_init(&ctrl->controller); INIT_LIST_HEAD(&ctrl->host_list); +#ifdef CONFIG_NAND_BRCMNAND_BCMBCA + /* + * BCMBCA platform does not use non-linux parameter-page-big-endian dts property, + * param page data is little endian + */ + ctrl->parameter_page_big_endian = 0; +#else /* Is parameter page in big endian ? */ ctrl->parameter_page_big_endian = dev_read_u32_default(dev, "parameter-page-big-endian", 1); +#endif /* NAND register range */ #ifndef __UBOOT__ From 5b70f26fed5aee9820530fd818f041d1779a4911 Mon Sep 17 00:00:00 2001 From: david regan Date: Tue, 12 Nov 2024 22:27:15 -0800 Subject: [PATCH 19/57] mtd: rawnand: brcmnand: update log level messages Update log level messages so that more critical messages can be logged to console and help the troubleshooting with field devices. This is a port of the upstream Linux patch to U-Boot. https://lore.kernel.org/linux-mtd/20240223034758.13753-4-william.zhang@broadcom.com/ Signed-off-by: david regan Reviewed-by: Linus Walleij Reviewed-by: William Zhang Reviewed-by: Anand Gore --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 7fd9e1855d1..ef492e6db32 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -1071,8 +1071,8 @@ static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, if ((val & mask) == expected_val) return 0; - dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", - expected_val, val & mask); + dev_err(ctrl->dev, "timeout on status poll (expected %x got %x)\n", + expected_val, val & mask); return -ETIMEDOUT; } @@ -2032,7 +2032,7 @@ try_dmaread: return err; } - dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", + dev_err(ctrl->dev, "uncorrectable error at 0x%llx\n", (unsigned long long)err_addr); mtd->ecc_stats.failed++; /* NAND layer expects zero on ECC errors */ From 91bc909d317cfef08cc263e406e747e40ad4ab6c Mon Sep 17 00:00:00 2001 From: Yuri Zaporozhets Date: Mon, 11 Nov 2024 20:24:04 +0100 Subject: [PATCH 20/57] spl: increase SPL_SYS_MALLOC_SIZE when using BIOSEMU on RISC-V If BIOSEMU is compiled for RISC-V (SiFive Unmatched board) and the function dm_pci_run_vga_bios() is executed, U-Boot stops with error message saying that the SPL malloc pool is too small. So increase the default pool size when both BIOSEMU and RISCV parameters are set. Signed-off-by: Yuri Zaporozhets Reviewed-by: Leo Yu-Chi Liang --- common/spl/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 045fcac10a5..240543c9c7e 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -462,6 +462,7 @@ config SPL_CUSTOM_SYS_MALLOC_ADDR config SPL_SYS_MALLOC_SIZE hex "Size of the SPL malloc pool" depends on SPL_SYS_MALLOC + default 0x180000 if BIOSEMU && RISCV default 0x100000 config SPL_READ_ONLY From afc52da8946909bfd21ea224281effc37440edfc Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 12 Nov 2024 11:42:23 +0100 Subject: [PATCH 21/57] configs: SiFive Unmatched: enable 'env erase' sub-command With the move from script based booting to using bootmeth a lot of environment variables have changed. To always use the default environment it is recommendable to erase the environment stored in the SPI flash. This can be done with the 'env erase' sub-command. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- configs/sifive_unmatched_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 058e5fab683..6fede360aeb 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -42,6 +42,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y +CONFIG_CMD_ERASEENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_PWM=y From 185986caebf623c11071db8cb1d94e0d82f1d9e7 Mon Sep 17 00:00:00 2001 From: Andreas Schwab Date: Tue, 12 Nov 2024 17:27:22 +0100 Subject: [PATCH 22/57] configs: visionfive2: re-enable SPL_SYS_MMCSD_RAW_MODE To restore MMC boot, enable SPL_SYS_MMCSD_RAW_MODE and recover SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION and SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION. Fixes: 2a00d73d081 ("spl: mmc: Try to clean up raw-mode options") Signed-off-by: Andreas Schwab Reviewed-by: Leo Yu-Chi Liang --- configs/starfive_visionfive2_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 20f89ae6796..319e1d358a0 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -56,6 +56,9 @@ CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2 CONFIG_SPL_SYS_MALLOC_SIZE=0x400000 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y From bdca70632dad38a1f7830c955771c0bd88ce7ae0 Mon Sep 17 00:00:00 2001 From: Yuri Zaporozhets Date: Tue, 19 Nov 2024 21:59:59 +0100 Subject: [PATCH 23/57] configs: enable CONFIG_PCI_REGION_MULTI_ENTRY=y in sifive_unmatched_defconfig Currently, the PCI subsystem selects the small "region 2" (which starts at 0x7000000) as bus_addr/phys_addr. As a consequence, the BAR0 on PCIe video card cannot be initialized, because it simply doesn't fit into 0x1000000 bytes size of "region 2". U-Boot should use "region 1" instead (the one which starts at 0x60090000), because it has much bigger size (0xFF70000), and easily accomodates BAR0 of the video card. Linux kernel also uses 0x60090000 as bus_start/phys_start. Signed-off-by: Yuri Zaporozhets Reviewed-by: Leo Yu-Chi Liang --- configs/sifive_unmatched_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 6fede360aeb..6f511796a20 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -36,6 +36,7 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ID_EEPROM=y CONFIG_PCI_INIT_R=y +CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_SPL_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y From 6e18eec9080b0a079fc33a2ac8a7e2dd753944ee Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 29 Nov 2024 01:13:53 +0100 Subject: [PATCH 24/57] ARM: dts: imx: Make DRAM coding GPIOs available before relocation on Data Modul i.MX8M Mini/Plus eDM SBC The DRAM configuration GPIO straps must be accessible in SPL and before relocation because the GPIOs are sampled both in U-Boot SPL as well as early on in U-Boot proper. The already present bootph-pre-ram DT property made the GPIO controllers available in SPL, but not early on in U-Boot proper, which made gpio_request_list_by_name_nodev() in board dmo_get_memcfg() fail. Add missing bootph-some-ram DT property to all GPIO controllers which are referenced in dmo,ram-coding-gpios DT property to make those GPIO controllers available early in U-Boot proper as well. Fixes: 8c103c33fb14 ("dm: dts: Convert driver model tags to use new schema") Signed-off-by: Marek Vasut --- arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi | 1 + arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi index a235e088fa4..fb6951026d9 100644 --- a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi @@ -77,6 +77,7 @@ &gpio2 { bootph-pre-ram; + bootph-some-ram; dsi-reset-hog { bootph-pre-ram; diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi index 805b5f57955..1e82e718b8f 100644 --- a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi @@ -64,6 +64,7 @@ &gpio3 { bootph-pre-ram; + bootph-some-ram; bl-enable-hog { bootph-pre-ram; @@ -92,6 +93,7 @@ &gpio4 { bootph-pre-ram; + bootph-some-ram; dsi-reset-hog { bootph-pre-ram; From 1171adfd89904eb4f299da22deaa0731ed5f2957 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 29 Nov 2024 01:13:54 +0100 Subject: [PATCH 25/57] ARM: dts: imx: Pick safe DRAM size on failure on Data Modul i.MX8M Mini/Plus eDM SBC In case gpio_request_list_by_name_nodev() in board dmo_get_memcfg() returns error code, pick a safe default DRAM configuration instead of bailing out with some sort of hang() or panic(). The BIT(2)|BIT(0) strap option is the lowest known option of 2 GiB , use that. Signed-off-by: Marek Vasut --- board/data_modul/common/common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/data_modul/common/common.c b/board/data_modul/common/common.c index b5f83908771..9e35dc5d6cb 100644 --- a/board/data_modul/common/common.c +++ b/board/data_modul/common/common.c @@ -47,6 +47,9 @@ u8 dmo_get_memcfg(void) "dmo,ram-coding-gpios", gpio, ARRAY_SIZE(gpio), GPIOD_IS_IN); + if (ret < 0) + return BIT(2) | BIT(0); + for (i = 0; i < ret; i++) memcfg |= !!dm_gpio_get_value(&(gpio[i])) << i; From ec3e5fa55d8232f3e5938a2702e20fa432600adf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 29 Nov 2024 01:13:55 +0100 Subject: [PATCH 26/57] ARM: imx: Perform plain boot in altbootcmd on Data Modul i.MX8M Mini/Plus eDM SBC The current A/B switching preparatory altbootcmd is confusing to users, replace it with plain 'run bootcmd' which can be replaced by proper A/B switching altbootcmd when the matching updater is added on top of the platform. By default, keep the boot counter incrementing, but do not do any A/B partition switching. Signed-off-by: Marek Vasut --- include/configs/imx8mm_data_modul_edm_sbc.h | 2 +- include/configs/imx8mp_data_modul_edm_sbc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index d323f84ac7a..57ecb5e2190 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -34,7 +34,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_EXTRA_ENV_SETTINGS \ - "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ + "altbootcmd=run bootcmd\0" \ "bootlimit=3\0" \ "devtype=mmc\0" \ "devpart=1\0" \ diff --git a/include/configs/imx8mp_data_modul_edm_sbc.h b/include/configs/imx8mp_data_modul_edm_sbc.h index f953847ce05..de5bdd30e18 100644 --- a/include/configs/imx8mp_data_modul_edm_sbc.h +++ b/include/configs/imx8mp_data_modul_edm_sbc.h @@ -24,7 +24,7 @@ #define FEC_QUIRK_ENET_MAC #define CFG_EXTRA_ENV_SETTINGS \ - "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ + "altbootcmd=run bootcmd\0" \ "bootlimit=3\0" \ "devtype=mmc\0" \ "devpart=1\0" \ From 3a689038bf9b8e841c68c8cc9f4b9ad484e814b2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 29 Nov 2024 01:13:56 +0100 Subject: [PATCH 27/57] ARM: imx: Deduplicate Data Modul i.MX8M eDM SBC defconfigs Deduplicate defconfigs for all Data Modul i.MX8M eDM SBC systems by factoring out the common parts into generic imx8m_data_modul.config and including those using the #include preprocessor macro in the current set of board specific defconfigs. The preprocessor macro is applicable to defconfigs as well. This introduces no functional change, the resulting .config is almost identical for all Data Modul i.MX8M eDM SBC systems, except for slight alignment in DEBUG_UART and SYS_PBSIZE. Signed-off-by: Marek Vasut --- configs/imx8m_data_modul.config | 221 +++++++++++++++ configs/imx8mm_data_modul_edm_sbc_defconfig | 262 ++--------------- configs/imx8mp_data_modul_edm_sbc_defconfig | 293 +++----------------- 3 files changed, 283 insertions(+), 493 deletions(-) create mode 100644 configs/imx8m_data_modul.config diff --git a/configs/imx8m_data_modul.config b/configs/imx8m_data_modul.config new file mode 100644 index 00000000000..2164c754915 --- /dev/null +++ b/configs/imx8m_data_modul.config @@ -0,0 +1,221 @@ +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_INPUT is not set +# CONFIG_SPI_FLASH_UNLOCK_ALL is not set +# CONFIG_SPL_DM_USB is not set +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_ARCH_IMX8M=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_ARM=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset" +CONFIG_BOOTCOUNT_BOOTLIMIT=3 +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_BKOPS_ENABLE=y +CONFIG_CMD_BOOTCOUNT=y +CONFIG_CMD_BTRFS=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_CAT=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_DHCP6=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_LSBLK=y +CONFIG_CMD_MBR=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y +CONFIG_CMD_PART=y +CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_PXE=y +CONFIG_CMD_READ=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_SMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_UUID=y +CONFIG_CMD_WGET=y +CONFIG_CMD_XXD=y +CONFIG_CONSOLE_MUX=y +CONFIG_CRC32_VERIFY=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x30880000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DFU_MMC=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_TIMEOUT=y +CONFIG_DM_ETH_PHY=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MDIO=y +CONFIG_DM_MTD=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_DM_RTC=y +CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_THERMAL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_OFFSET=0xFFFC0000 +CONFIG_ENV_OFFSET_REDUND=0xFFFC0000 +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FEC_MXC=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_FSL_CAAM=y +CONFIG_FSL_USDHC=y +CONFIG_GPIO_HOG=y +CONFIG_HASH_VERIFY=y +CONFIG_HUSH_PARSER=y +CONFIG_I2C_EEPROM=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX_BOOTAUX=y +CONFIG_IMX_TMU=y +CONFIG_IMX_WATCHDOG=y +CONFIG_IPV6=y +CONFIG_IP_DEFRAG=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_MII=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_SPEED_MODE_SET=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MTD=y +CONFIG_MTDIDS_DEFAULT="nor0=flash@0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)" +CONFIG_MXC_GPIO=y +CONFIG_MXC_SPI=y +CONFIG_MXC_UART=y +CONFIG_NETCONSOLE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_OF_CONTROL=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_PHY_ANEG_TIMEOUT=20000 +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_BROADCOM=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_PROT_TCP_SACK=y +CONFIG_REGMAP=y +CONFIG_RGMII=y +CONFIG_RTC_M41T62=y +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SHA1SUM_VERIFY=y +CONFIG_SPI=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPL=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_GPIO=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_I2C=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_MMC=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_PINCTRL=y +CONFIG_SPL_POWER=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_SYSRESET=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYSCON=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 +CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 +CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y +CONFIG_SYS_BOOTM_LEN=0x8000000 +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 +CONFIG_SYS_EEPROM_SIZE=16384 +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_MALLOC_LEN=0x1000000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_SYS_MONITOR_LEN=1048576 +CONFIG_SYS_PBSIZE=2081 +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_TFTP_TSIZE=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_FUNCTION_ACM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Data Modul" +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_HUB_USB251XB=y +CONFIG_USB_STORAGE=y +CONFIG_USE_BOOTARGS=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_USE_PREBOOT=y +CONFIG_VERSION_VARIABLE=y diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index 105fbfb4d9b..7c9d4ee1844 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -1,242 +1,28 @@ +#include + CONFIG_ARM=y CONFIG_ARCH_IMX8M=y -CONFIG_TEXT_BASE=0x40200000 -CONFIG_SYS_MALLOC_LEN=0x1000000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SF_DEFAULT_SPEED=50000000 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_OFFSET=0xFFFC0000 -CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg" -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mm-data-modul-edm-sbc" CONFIG_TARGET_IMX8MM_DATA_MODUL_EDM_SBC=y -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_DM_RESET=y -CONFIG_SYS_MONITOR_LEN=1048576 -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 -CONFIG_SPL_STACK=0x920000 -CONFIG_SPL_TEXT_BASE=0x7E1000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x910000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SYS_BOOTM_LEN=0x8000000 -CONFIG_SYS_LOAD_ADDR=0x60000000 -CONFIG_SPL=y -CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_ENV_OFFSET_REDUND=0xFFFC0000 -CONFIG_IMX_BOOTAUX=y -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_FIT=y -CONFIG_FIT_EXTERNAL_OFFSET=0x3000 -CONFIG_SPL_LOAD_FIT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_USE_BOOTARGS=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset" -CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="run dmo_preboot" -CONFIG_DEFAULT_FDT_FILE="imx8mm-data-modul-edm-sbc.dtb" -CONFIG_SYS_CBSIZE=2048 -CONFIG_SYS_PBSIZE=2074 -CONFIG_CONSOLE_MUX=y -CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_LATE_INIT=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -CONFIG_SPL_LEGACY_IMAGE_FORMAT=y -CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 -CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 -CONFIG_SPL_I2C=y -CONFIG_SPL_POWER=y -CONFIG_SPL_RAM_DEVICE=y -CONFIG_SPL_WATCHDOG=y -CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="u-boot=> " -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_EXPORTENV is not set -CONFIG_CMD_ERASEENV=y -CONFIG_CRC32_VERIFY=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_SIZE=16384 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 -CONFIG_CMD_MD5SUM=y -CONFIG_MD5SUM_VERIFY=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_SHA1SUM=y -CONFIG_SHA1SUM_VERIFY=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FUSE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_GPT_RENAME=y -CONFIG_CMD_I2C=y -CONFIG_CMD_LSBLK=y -CONFIG_CMD_MBR=y -CONFIG_CMD_MMC=y -CONFIG_CMD_BKOPS_ENABLE=y -CONFIG_MMC_SPEED_MODE_SET=y -CONFIG_CMD_MTD=y -CONFIG_CMD_PART=y -CONFIG_CMD_READ=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_SDP=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_CAT=y -CONFIG_CMD_XXD=y -CONFIG_CMD_DHCP6=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_WGET=y -CONFIG_CMD_PXE=y -CONFIG_CMD_BOOTCOUNT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_GETTIME=y -CONFIG_CMD_KASLRSEED=y -CONFIG_CMD_SYSBOOT=y -CONFIG_CMD_UUID=y -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y -CONFIG_CMD_SMC=y -CONFIG_HASH_VERIFY=y -CONFIG_CMD_BTRFS=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_FS_UUID=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y -CONFIG_MTDIDS_DEFAULT="nor0=flash@0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)" -CONFIG_PARTITION_TYPE_GUID=y -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_IP_DEFRAG=y -CONFIG_TFTP_TSIZE=y -CONFIG_PROT_TCP_SACK=y -CONFIG_IPV6=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_REGMAP=y -CONFIG_SYSCON=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 -CONFIG_SPL_CLK_COMPOSITE_CCF=y -CONFIG_CLK_COMPOSITE_CCF=y -CONFIG_SPL_CLK_IMX8MM=y -CONFIG_CLK_IMX8MM=y -CONFIG_FSL_CAAM=y -CONFIG_DFU_TFTP=y -CONFIG_DFU_TIMEOUT=y -CONFIG_DFU_MMC=y -CONFIG_DFU_MTD=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x42800000 -CONFIG_FASTBOOT_BUF_SIZE=0x20000000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_GPIO_HOG=y -CONFIG_MXC_GPIO=y -CONFIG_DM_I2C=y -# CONFIG_INPUT is not set -CONFIG_USB_HUB_USB251XB=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_IO_VOLTAGE=y -CONFIG_SPL_MMC_IO_VOLTAGE=y -CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS400_ES_SUPPORT=y -CONFIG_MMC_HS400_SUPPORT=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_SFDP_SUPPORT=y -# CONFIG_SPI_FLASH_UNLOCK_ALL is not set -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_PHYLIB=y -CONFIG_PHY_ANEG_TIMEOUT=20000 -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_DM_MDIO=y -CONFIG_DM_ETH_PHY=y -CONFIG_FEC_MXC=y -CONFIG_RGMII=y -CONFIG_MII=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_IMX8M=y -CONFIG_POWER_DOMAIN=y -CONFIG_IMX8M_POWER_DOMAIN=y -CONFIG_DM_PMIC=y -CONFIG_DM_PMIC_BD71837=y -CONFIG_SPL_DM_PMIC_BD71837=y -CONFIG_DM_REGULATOR=y -CONFIG_SPL_DM_REGULATOR=y -CONFIG_DM_REGULATOR_BD71837=y -CONFIG_SPL_DM_REGULATOR_BD71837=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_DM_RNG=y -CONFIG_DM_RTC=y -CONFIG_RTC_M41T62=y -CONFIG_DM_SERIAL=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_MXC_SPI=y -CONFIG_SYSRESET=y -CONFIG_SPL_SYSRESET=y -CONFIG_SYSRESET_PSCI=y -CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_TMU=y -CONFIG_USB=y -# CONFIG_SPL_DM_USB is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Data Modul" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y -CONFIG_USB_FUNCTION_ACM=y -CONFIG_IMX_WATCHDOG=y +CONFIG_CLK_IMX8MM=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-data-modul-edm-sbc" +CONFIG_DEFAULT_FDT_FILE="imx8mm-data-modul-edm-sbc.dtb" +CONFIG_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR_BD71837=y +CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg" +CONFIG_PHYLIB=y +CONFIG_PREBOOT="run dmo_preboot" +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_CLK_IMX8MM=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_SPL_DM_REGULATOR_BD71837=y +CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y +CONFIG_SPL_LEGACY_IMAGE_FORMAT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_STACK=0x920000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_LOAD_ADDR=0x60000000 diff --git a/configs/imx8mp_data_modul_edm_sbc_defconfig b/configs/imx8mp_data_modul_edm_sbc_defconfig index f809d23d6d2..ea8109bf049 100644 --- a/configs/imx8mp_data_modul_edm_sbc_defconfig +++ b/configs/imx8mp_data_modul_edm_sbc_defconfig @@ -1,271 +1,54 @@ +#include + CONFIG_ARM=y CONFIG_ARCH_IMX8M=y -CONFIG_TEXT_BASE=0x40200000 -CONFIG_SYS_MALLOC_LEN=0x1000000 -CONFIG_SYS_MALLOC_F_LEN=0x18000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SF_DEFAULT_SPEED=50000000 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_OFFSET=0xFFFC0000 -CONFIG_DM_GPIO=y -CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mp-data-modul-edm-sbc" CONFIG_TARGET_IMX8MP_DATA_MODUL_EDM_SBC=y -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_DM_RESET=y -CONFIG_SYS_MONITOR_LEN=1048576 -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 -CONFIG_SPL_STACK=0x96fc00 -CONFIG_SPL_TEXT_BASE=0x920000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x96fc00 -CONFIG_SPL_BSS_MAX_SIZE=0x400 -CONFIG_SYS_BOOTM_LEN=0x8000000 -CONFIG_SYS_LOAD_ADDR=0x50000000 -CONFIG_SPL=y -CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y -CONFIG_DEBUG_UART_BASE=0x30880000 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_ENV_OFFSET_REDUND=0xFFFC0000 -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI=y -CONFIG_IMX_BOOTAUX=y -CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 -CONFIG_DEBUG_UART=y -CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_FIT=y -CONFIG_FIT_EXTERNAL_OFFSET=0x3000 -CONFIG_SPL_LOAD_FIT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_USE_BOOTARGS=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset" -CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="imx8mp-data-modul-edm-sbc.dtb" -CONFIG_SYS_CBSIZE=2048 -CONFIG_SYS_PBSIZE=2081 -CONFIG_CONSOLE_MUX=y -CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y -CONFIG_ARCH_MISC_INIT=y -CONFIG_BOARD_LATE_INIT=y -CONFIG_SPL_MAX_SIZE=0x25000 -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_BOOTROM_SUPPORT=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 -CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 -CONFIG_SPL_I2C=y -CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_POWER=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000 -CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="u-boot=> " -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_EXPORTENV is not set -CONFIG_CMD_ERASEENV=y -CONFIG_CRC32_VERIFY=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_SIZE=16384 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20 -CONFIG_CMD_MD5SUM=y -CONFIG_MD5SUM_VERIFY=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_SHA1SUM=y -CONFIG_SHA1SUM_VERIFY=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FUSE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_GPT_RENAME=y -CONFIG_CMD_I2C=y -CONFIG_CMD_LSBLK=y -CONFIG_CMD_MBR=y -CONFIG_CMD_MMC=y -CONFIG_CMD_BKOPS_ENABLE=y -CONFIG_MMC_SPEED_MODE_SET=y -CONFIG_CMD_MTD=y -CONFIG_CMD_PART=y -CONFIG_CMD_READ=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_SDP=y -CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_CAT=y -CONFIG_CMD_XXD=y -CONFIG_CMD_DHCP6=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_WGET=y -CONFIG_CMD_PXE=y -CONFIG_CMD_BOOTCOUNT=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_GETTIME=y -CONFIG_CMD_KASLRSEED=y -CONFIG_CMD_SYSBOOT=y -CONFIG_CMD_UUID=y -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y -CONFIG_CMD_SMC=y -CONFIG_HASH_VERIFY=y -CONFIG_CMD_BTRFS=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_FS_UUID=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y -CONFIG_MTDIDS_DEFAULT="nor0=flash@0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)" -CONFIG_PARTITION_TYPE_GUID=y -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_NOWHERE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_IP_DEFRAG=y -CONFIG_TFTP_TSIZE=y -CONFIG_PROT_TCP_SACK=y -CONFIG_IPV6=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_REGMAP=y -CONFIG_SYSCON=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000 -CONFIG_SPL_CLK_COMPOSITE_CCF=y -CONFIG_CLK_COMPOSITE_CCF=y -CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y -CONFIG_FSL_CAAM=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-data-modul-edm-sbc" +CONFIG_DEFAULT_FDT_FILE="imx8mp-data-modul-edm-sbc.dtb" +CONFIG_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_DM_USB_GADGET=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y CONFIG_IMX8M_DRAM_INLINE_ECC=y -CONFIG_DFU_TFTP=y -CONFIG_DFU_TIMEOUT=y -CONFIG_DFU_MMC=y -CONFIG_DFU_MTD=y -CONFIG_DFU_RAM=y -CONFIG_USB_FUNCTION_FASTBOOT=y -CONFIG_FASTBOOT_BUF_ADDR=0x42800000 -CONFIG_FASTBOOT_BUF_SIZE=0x20000000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_GPIO_HOG=y -CONFIG_SPL_GPIO_HOG=y -CONFIG_MXC_GPIO=y -CONFIG_DM_I2C=y -# CONFIG_INPUT is not set CONFIG_LED=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y -CONFIG_USB_HUB_USB251XB=y -CONFIG_I2C_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_IO_VOLTAGE=y -CONFIG_SPL_MMC_IO_VOLTAGE=y -CONFIG_MMC_UHS_SUPPORT=y -CONFIG_SPL_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS400_ES_SUPPORT=y -CONFIG_MMC_HS400_SUPPORT=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_SFDP_SUPPORT=y -# CONFIG_SPI_FLASH_UNLOCK_ALL is not set -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_PHY_ANEG_TIMEOUT=20000 -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y +CONFIG_PHY_IMX8MQ_USB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_DM_MDIO=y -CONFIG_DM_ETH_PHY=y -CONFIG_DWC_ETH_QOS=y -CONFIG_DWC_ETH_QOS_IMX=y -CONFIG_FEC_MXC=y -CONFIG_RGMII=y -CONFIG_MII=y -CONFIG_PHY_IMX8MQ_USB=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_IMX8M=y -CONFIG_POWER_DOMAIN=y -CONFIG_IMX8M_POWER_DOMAIN=y -CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y -CONFIG_DM_PMIC=y -CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_BSS_MAX_SIZE=0x400 +CONFIG_SPL_BSS_START_ADDR=0x96fc00 +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000 CONFIG_SPL_DM_PMIC_PCA9450=y -CONFIG_DM_REGULATOR=y -CONFIG_SPL_DM_REGULATOR=y -CONFIG_DM_REGULATOR_PCA9450=y CONFIG_SPL_DM_REGULATOR_PCA9450=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_DM_RNG=y -CONFIG_DM_RTC=y -CONFIG_RTC_M41T62=y -CONFIG_DM_SERIAL=y -CONFIG_MXC_UART=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_MXC_SPI=y -CONFIG_SYSRESET=y -CONFIG_SPL_SYSRESET=y -CONFIG_SYSRESET_PSCI=y -CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_TMU=y -CONFIG_USB=y -# CONFIG_SPL_DM_USB is not set -CONFIG_DM_USB_GADGET=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y -CONFIG_USB_EHCI_HCD=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_GPIO_HOG=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_SPL_MAX_SIZE=0x25000 +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_STACK=0x96fc00 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_SYS_LOAD_ADDR=0x50000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000 CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_STORAGE=y -CONFIG_USB_HOST_ETHER=y -CONFIG_USB_ETHER_ASIX=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Data Modul" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_USB_FUNCTION_ACM=y CONFIG_USB_ETHER=y +CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETH_CDC=y -CONFIG_IMX_WATCHDOG=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_XHCI_HCD=y From 0b97a394f6b76dc0b538e23af0589a51717119c1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 29 Nov 2024 03:41:47 +0100 Subject: [PATCH 28/57] ARM: imx: Replace YModem with SDP on Data Modul i.MX8M Mini eDM SBC SPL The YModem support in SPL was never really used on this device, the SDP support is much more convenient on i.MX8M Mini based hardware. Replace the YModem support with SDP support. The SDP can be utilized by forcing the board into SDP boot mode by grounding test point right next to silkscreen label U30, and then by using mfgtools 'uuu -brun spl flash.bin' once the device enumerates on host system USB bus. The SDP capable USB port is available on the USB micro-B port on the base board. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan --- arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi | 9 +++++++++ board/data_modul/imx8mm_edm_sbc/spl.c | 6 ++++-- configs/imx8mm_data_modul_edm_sbc_defconfig | 7 ++++++- 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi index fb6951026d9..f5e98bf7487 100644 --- a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi @@ -145,8 +145,17 @@ bootph-pre-ram; }; +&usbmisc1 { + bootph-pre-ram; +}; + +&usbphynop1 { + bootph-pre-ram; +}; + &usbotg1 { dr_mode = "peripheral"; + bootph-pre-ram; }; &usdhc2 { diff --git a/board/data_modul/imx8mm_edm_sbc/spl.c b/board/data_modul/imx8mm_edm_sbc/spl.c index 17aafd719c9..a9ef049652a 100644 --- a/board/data_modul/imx8mm_edm_sbc/spl.c +++ b/board/data_modul/imx8mm_edm_sbc/spl.c @@ -61,8 +61,10 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) { if (boot_dev_spl == MMC3_BOOT) return BOOT_DEVICE_MMC2; /* eMMC */ - else + else if (boot_dev_spl == MMC2_BOOT) return BOOT_DEVICE_MMC1; /* SD */ + else + return BOOT_DEVICE_BOARD; } void board_boot_order(u32 *spl_boot_list) @@ -76,7 +78,7 @@ void board_boot_order(u32 *spl_boot_list) else spl_boot_list[1] = BOOT_DEVICE_MMC1; /* SD */ - spl_boot_list[2] = BOOT_DEVICE_UART; /* YModem */ + spl_boot_list[2] = BOOT_DEVICE_BOARD; /* SDP */ spl_boot_list[3] = BOOT_DEVICE_NONE; } diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index 7c9d4ee1844..518243e6513 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -12,17 +12,22 @@ CONFIG_DM_REGULATOR_BD71837=y CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg" CONFIG_PHYLIB=y CONFIG_PREBOOT="run dmo_preboot" +CONFIG_SDP_LOADADDR=0x60000000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BSS_START_ADDR=0x910000 +CONFIG_SPL_MAX_SIZE=0x30000 CONFIG_SPL_CLK_IMX8MM=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_SPL_DM_REGULATOR_BD71837=y +CONFIG_SPL_DM_USB=y CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y CONFIG_SPL_LEGACY_IMAGE_FORMAT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_STACK=0x920000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_TEXT_BASE=0x7E1000 -CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_HOST=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_LOAD_ADDR=0x60000000 From 4835efca7a004fab62853f3e6bbd2854d1df503b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 29 Nov 2024 01:35:43 +0100 Subject: [PATCH 29/57] ARM: dts: imx: Enable PCIe and NVMe on Data Modul i.MX8M Mini eDM SBC Enable PCIe/NVMe support on Data Modul i.MX8M Mini eDM SBC. Except for the configuration options which are enabled, add slight adjustment to board u-boot.dtsi, which is necessary as there is currently no driver for the I2C PCIe clock generator. Since the generator is strapped to be always on, it is possible to supplant the generator functionality by fixed-clock. Signed-off-by: Marek Vasut --- .../arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi | 15 +++++++++++++++ configs/imx8mm_data_modul_edm_sbc_defconfig | 6 ++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi index f5e98bf7487..3a4f7d01b9e 100644 --- a/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi @@ -16,6 +16,12 @@ dmo,ram-coding-gpios = <&gpio2 8 0>, <&gpio2 1 0>, <&gpio2 0 0>; }; + clk_pcie100: clk-pcie100 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; @@ -35,6 +41,15 @@ bootph-pre-ram; }; +&pcie_phy { + clocks = <&clk_pcie100>; +}; + +&pcie0 { + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk_pcie100>; +}; + &pinctrl_hog_sbc { bootph-pre-ram; }; diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index 518243e6513..66cb1331ded 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -5,12 +5,18 @@ CONFIG_ARCH_IMX8M=y CONFIG_TARGET_IMX8MM_DATA_MODUL_EDM_SBC=y CONFIG_CI_UDC=y CONFIG_CLK_IMX8MM=y +CONFIG_CMD_PCI=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-data-modul-edm-sbc" CONFIG_DEFAULT_FDT_FILE="imx8mm-data-modul-edm-sbc.dtb" CONFIG_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR_BD71837=y CONFIG_IMX_CONFIG="board/data_modul/imx8mm_edm_sbc/imximage.cfg" +CONFIG_NVME_PCI=y +CONFIG_PCI=y +CONFIG_PCIE_DW_IMX=y +CONFIG_PHY=y CONFIG_PHYLIB=y +CONFIG_PHY_IMX8M_PCIE=y CONFIG_PREBOOT="run dmo_preboot" CONFIG_SDP_LOADADDR=0x60000000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 From 6ceb861882b1583a12537e6c1b1391b16496ce33 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 29 Nov 2024 07:50:33 -0600 Subject: [PATCH 30/57] Revert "arm64: dts: ti: k3-j7200: Fix OSPI boot" While I had thought this commit was a cherry-pick from upstream, it is not. And so, this is not allowed here. This reverts commit dfe5f16a33453b742a66cabc8ea9a52a33279810. Signed-off-by: Tom Rini --- dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi index 014cf1805fb..21fe194a576 100644 --- a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi +++ b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi @@ -124,7 +124,6 @@ }; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { - bootph-all; pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ From 20f641987f83c4679a1181d79a546a098f11f5ad Mon Sep 17 00:00:00 2001 From: Jerome Forissier Date: Fri, 15 Nov 2024 17:45:14 +0100 Subject: [PATCH 31/57] test/cmd/wget.c: move net_test_wget() to the cmd test suite Since net_test_wget() is testing a command and is in test/cmd it should be in the 'cmd' test suite, not 'lib'. Saving and restoring the values of the environment variables that the test manipulates is necessary to avoid a regression when running the whole ut test suite. A minimal reproducer is: $ ./u-boot -T -c "ut cmd net_test_wget; ut dm dm_test_eth_act" | \ grep -E "(Test:|Failures:)" Reported-by: Simon Glass Signed-off-by: Jerome Forissier --- test/cmd/wget.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/test/cmd/wget.c b/test/cmd/wget.c index fe26fee54c9..7570c065a10 100644 --- a/test/cmd/wget.c +++ b/test/cmd/wget.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include @@ -206,6 +206,10 @@ static int sb_http_handler(struct udevice *dev, void *packet, static int net_test_wget(struct unit_test_state *uts) { + char *prev_ethact = env_get("ethact"); + char *prev_ethrotate = env_get("ethrotate"); + char *prev_loadaddr = env_get("loadaddr"); + sandbox_eth_set_tx_handler(0, sb_http_handler); sandbox_eth_set_priv(0, uts); @@ -223,6 +227,10 @@ static int net_test_wget(struct unit_test_state *uts) ut_assert_nextline("md5 for 00020000 ... 0002001f ==> 234af48e94b0085060249ecb5942ab57"); ut_assert_console_end(); + env_set("ethact", prev_ethact); + env_set("ethrotate", prev_ethrotate); + env_set("loadaddr", prev_loadaddr); + return 0; } -LIB_TEST(net_test_wget, UTF_CONSOLE); +CMD_TEST(net_test_wget, UTF_CONSOLE); From 65b38a519b0fcae6a76f48116a5f999400d7294c Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 29 Nov 2024 19:08:13 +0200 Subject: [PATCH 32/57] Revert "efi_memory: do not add U-Boot memory to the memory map" This reverts commit ("commit a68c9ac5d8af ("efi_memory: do not add U-Boot memory to the memory map"). This code was removed when the EFI subsystem started using LMB calls for the reservations. In hindsight it unearthed two problems. The e820 code is adding u-boot memory as EfiReservedMemory while it should look at what LMB added and decide instead of blindly overwriting it. The reason this worked is that we marked that code properly late, when the EFI came up. But now with the LMB changes, the EFI map gets added first and the e820 code overwrites it. The second problem is that we never mark SetVirtualAddressMap as runtime code, which we should according to the spec. Until we fix this the current hack can't go away, at least for architectures that *need* to call SVAM. More specifically x86 currently requires SVAM and sets the NX bit for pages not marked as *_CODE. So unless we do that late, it will crash trying to execute from non-executable memory. It's also worth noting that x86 calls SVAM late in the boot, so this will work until someone decides to overwrite/use BootServicesCode from the OS. Notably arm64 disables it explicitly if the VA space is > 48bits, so doesn't suffer from any of these problems. This doesn't really deserve a fixes tag, since it brings back a hack to remedy a situation that was wrong long before that commit, but in case anyone hits the same bug ... Simon sent the original revert in the link, but we need a proper justification for it. Link: https://lore.kernel.org/u-boot/20241112131830.576864-1-sjg@chromium.org/ Signed-off-by: Ilias Apalodimas Acked-by: Sughosh Ganu Reported-by: Simon Glass --- lib/efi_loader/efi_memory.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index e493934c713..edd7da7d8c6 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -814,7 +814,16 @@ static void add_u_boot_and_runtime(void) { unsigned long runtime_start, runtime_end, runtime_pages; unsigned long runtime_mask = EFI_PAGE_MASK; + unsigned long uboot_start, uboot_pages; + unsigned long uboot_stack_size = CONFIG_STACK_SIZE; + /* Add U-Boot */ + uboot_start = ((uintptr_t)map_sysmem(gd->start_addr_sp, 0) - + uboot_stack_size) & ~EFI_PAGE_MASK; + uboot_pages = ((uintptr_t)map_sysmem(gd->ram_top - 1, 0) - + uboot_start + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; + efi_add_memory_map_pg(uboot_start, uboot_pages, EFI_BOOT_SERVICES_CODE, + false); #if defined(__aarch64__) /* * Runtime Services must be 64KiB aligned according to the From a37064cb2e482739908e76d6a53914301c8bb8ee Mon Sep 17 00:00:00 2001 From: Jerome Forissier Date: Tue, 26 Nov 2024 15:45:06 +0100 Subject: [PATCH 33/57] net: lwip: wget: fix legacy syntax Commit 356011f7ac25 ("lwip: fix code style issues") has inadvertently broken the support for the legacy syntax: => wget 192.168.0.16:test.bin invalid uri, no file path Invalid URL. Use http(s):// The reason is two calls to strncpy() were replaced by strlcpy() without paying attention to the fact that they are not equivalent in the present case. Since we are using a character counter (n) and since we do not depend on having a properly null-terminated string at each step in the parsing, strlcpy() is not justified and strncpy() is the right tool for the job. So use it again. Reported-by: Tom Rini Signed-off-by: Jerome Forissier --- net/lwip/wget.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/lwip/wget.c b/net/lwip/wget.c index 062aa7c44f0..5501ffdd004 100644 --- a/net/lwip/wget.c +++ b/net/lwip/wget.c @@ -161,7 +161,7 @@ static int parse_legacy_arg(char *arg, char *nurl, size_t rem) if (rem < n) return -1; - strlcpy(p, server, n); + strncpy(p, server, n); p += n; rem -= n; if (rem < 1) @@ -172,7 +172,7 @@ static int parse_legacy_arg(char *arg, char *nurl, size_t rem) n = strlen(path); if (rem < n) return -1; - strlcpy(p, path, n); + strncpy(p, path, n); p += n; rem -= n; if (rem < 1) From 57b6fb7eb1f8fc4e80418006db0611e4c365623b Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Tue, 26 Nov 2024 20:12:14 +0100 Subject: [PATCH 34/57] Makefile: avoid non-standard sed expressions The '?' that is used in the sed expression that determines MK_ARCH is part of the extended regular expression syntax, but the default behaviour of sed as specified by POSIX is to use only basic regular expression syntax. Use the equivalent '\{0,1\}' instead as suggested by the OpenBSD re_format(7) man page. Fixes: 04b1d84221d5 ("Makefile: fix empty MK_ARCH when using ccache") Signed-off-by: Mark Kettenis Reviewed-by: Marek Vasut Tested-by: Quentin Schulz --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 22953bdabd8..7933ade6eff 100644 --- a/Makefile +++ b/Makefile @@ -21,7 +21,7 @@ include include/host_arch.h ifeq ("", "$(CROSS_COMPILE)") MK_ARCH="${shell uname -m}" else - MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(ccache\)\?[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}" + MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}" endif unexport HOST_ARCH ifeq ("x86_64", $(MK_ARCH)) From 6e3e72ed4e9632d23d8f1567cfc1c71d70c7a72a Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Mon, 25 Nov 2024 10:33:22 +0100 Subject: [PATCH 35/57] arm: dts: socfpga: remove spurious execute permission from dt files It doesn't make sense for these files to have the x bit set. It was, probably accidentally, added in: Fixes: 2c494e62c31a (arm: dts: Stratix10: Add QSPI node) Signed-off-by: Rasmus Villemoes --- arch/arm/dts/socfpga_stratix10.dtsi | 0 arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 0 arch/arm/dts/socfpga_stratix10_socdk.dts | 0 3 files changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi mode change 100755 => 100644 arch/arm/dts/socfpga_stratix10_socdk.dts diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi old mode 100755 new mode 100644 diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi old mode 100755 new mode 100644 diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts old mode 100755 new mode 100644 From 12fcb9825758a6ad84a22999eaaaa4a0c6a8ff94 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Mon, 25 Nov 2024 10:37:00 +0100 Subject: [PATCH 36/57] powerpc/t2080qds: remove spurious x permission from README file It doesn't make sense for a README file to be executable. Remove that bit. Signed-off-by: Rasmus Villemoes --- board/freescale/t208xqds/README | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 board/freescale/t208xqds/README diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README old mode 100755 new mode 100644 From 03e57244bc260da9b9839d387cc5eb691f88b5bd Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 1 Dec 2024 07:42:34 -0700 Subject: [PATCH 37/57] binman: Avoid skipping binman_init() A recent lwip change stopped binman's init from working, so it is not possible to read nodes from the image description anymore. Correct this by dropping the offending line. Signed-off-by: Simon Glass Fixes: 4d4d7838127 net: lwip: add TFTP support and tftpboot command --- lib/binman.c | 1 - 1 file changed, 1 deletion(-) diff --git a/lib/binman.c b/lib/binman.c index 93d85548116..9047f5275f3 100644 --- a/lib/binman.c +++ b/lib/binman.c @@ -137,7 +137,6 @@ int binman_init(void) { int ret; - return 0; binman = malloc(sizeof(struct binman_info)); if (!binman) return log_msg_ret("space for binman", -ENOMEM); From 924a5e4e41e99cefabc465c82ffd91374d38a1e7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 1 Dec 2024 07:42:35 -0700 Subject: [PATCH 38/57] Revert "global_data: Drop spl_handoff" This breaks chromebook_coral which says: Video: No video mode configured in FSP! This reverts commit 2e9313179a846b581c0fc3f6a49e19f3d343efa8. Signed-off-by: Simon Glass --- arch/x86/cpu/intel_common/cpu_from_spl.c | 4 +++- arch/x86/lib/fsp2/fsp_dram.c | 4 ++-- cmd/sb.c | 6 ++---- common/board_f.c | 12 ++++++++++++ common/init/handoff.c | 12 ------------ drivers/clk/rockchip/clk_rk3399.c | 3 +-- include/asm-generic/global_data.h | 6 ++++++ include/handoff.h | 7 ------- 8 files changed, 26 insertions(+), 28 deletions(-) diff --git a/arch/x86/cpu/intel_common/cpu_from_spl.c b/arch/x86/cpu/intel_common/cpu_from_spl.c index 5aad2ae7309..48b2ef253cb 100644 --- a/arch/x86/cpu/intel_common/cpu_from_spl.c +++ b/arch/x86/cpu/intel_common/cpu_from_spl.c @@ -24,7 +24,9 @@ int arch_cpu_init(void) int ret; #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB) - gd->arch.hob_list = handoff_get(); + struct spl_handoff *ho = gd->spl_handoff; + + gd->arch.hob_list = ho->arch.hob_list; #endif ret = x86_cpu_reinit_f(); diff --git a/arch/x86/lib/fsp2/fsp_dram.c b/arch/x86/lib/fsp2/fsp_dram.c index 4c4c8334bdb..75fa8f9de7a 100644 --- a/arch/x86/lib/fsp2/fsp_dram.c +++ b/arch/x86/lib/fsp2/fsp_dram.c @@ -59,7 +59,7 @@ int dram_init(void) #endif } else { #if CONFIG_IS_ENABLED(HANDOFF) - struct spl_handoff *ho = handoff_get(); + struct spl_handoff *ho = gd->spl_handoff; if (!ho) { log_debug("No SPL handoff found\n"); @@ -82,7 +82,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_size; #if CONFIG_IS_ENABLED(HANDOFF) - struct spl_handoff *ho = handoff_get(); + struct spl_handoff *ho = gd->spl_handoff; log_debug("usable_ram_top = %lx\n", ho->arch.usable_ram_top); diff --git a/cmd/sb.c b/cmd/sb.c index 9245052492e..79f3fb0aacd 100644 --- a/cmd/sb.c +++ b/cmd/sb.c @@ -15,10 +15,8 @@ static int do_sb_handoff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { #if CONFIG_IS_ENABLED(HANDOFF) - struct spl_handoff *handoff = handoff_get(); - - if (handoff) - printf("SPL handoff magic %lx\n", handoff->arch.magic); + if (gd->spl_handoff) + printf("SPL handoff magic %lx\n", gd->spl_handoff->arch.magic); else printf("SPL handoff info not received\n"); diff --git a/common/board_f.c b/common/board_f.c index 98dc2591e1d..939697d13d8 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -305,6 +305,17 @@ static int setup_mon_len(void) return 0; } +static int setup_spl_handoff(void) +{ +#if CONFIG_IS_ENABLED(HANDOFF) + gd->spl_handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, + sizeof(struct spl_handoff)); + debug("Found SPL hand-off info %p\n", gd->spl_handoff); +#endif + + return 0; +} + __weak int arch_cpu_init(void) { return 0; @@ -880,6 +891,7 @@ static const init_fnc_t init_sequence_f[] = { initf_bootstage, /* uses its own timer, so does not need DM */ event_init, bloblist_maybe_init, + setup_spl_handoff, #if defined(CONFIG_CONSOLE_RECORD_INIT_F) console_record_init, #endif diff --git a/common/init/handoff.c b/common/init/handoff.c index 86c020ee0b9..a7cd065fb38 100644 --- a/common/init/handoff.c +++ b/common/init/handoff.c @@ -5,7 +5,6 @@ * Copyright 2018 Google, Inc */ -#include #include #include @@ -39,14 +38,3 @@ void handoff_load_dram_banks(struct spl_handoff *ho) bd->bi_dram[i].size = ho->ram_bank[i].size; } } - -struct spl_handoff *handoff_get(void) -{ - struct spl_handoff *handoff; - - handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, - sizeof(struct spl_handoff)); - debug("Found SPL hand-off info %p\n", handoff); - - return handoff; -} diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 155ea8d6353..6e87db18be0 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -1468,7 +1467,7 @@ static int rk3399_clk_probe(struct udevice *dev) init_clocks = true; #elif CONFIG_IS_ENABLED(HANDOFF) if (!(gd->flags & GD_FLG_RELOC)) { - if (!handoff_get()) + if (!(gd->spl_handoff)) init_clocks = true; } #endif diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 26277b93976..789adf2c3f9 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -400,6 +400,12 @@ struct global_data { */ struct bloblist_hdr *bloblist; #endif +#if CONFIG_IS_ENABLED(HANDOFF) + /** + * @spl_handoff: SPL hand-off information + */ + struct spl_handoff *spl_handoff; +#endif #if defined(CONFIG_TRANSLATION_OFFSET) /** * @translation_offset: optional translation offset diff --git a/include/handoff.h b/include/handoff.h index 0072ea832f8..c0ae7b19a75 100644 --- a/include/handoff.h +++ b/include/handoff.h @@ -31,13 +31,6 @@ void handoff_save_dram(struct spl_handoff *ho); void handoff_load_dram_size(struct spl_handoff *ho); void handoff_load_dram_banks(struct spl_handoff *ho); -/** - * handoff_get() - Get the SPL handoff information - * - * Return: Pointer to SPL handoff if received, else NULL - */ -struct spl_handoff *handoff_get(void); - /** * handoff_arch_save() - Save arch-specific info into the handoff area * From acab6e78aca767ef71470871842e5c090e3672c7 Mon Sep 17 00:00:00 2001 From: Evgeny Bachinin Date: Mon, 25 Nov 2024 12:15:07 +0300 Subject: [PATCH 39/57] common: relocate fdt_blob in global_data for FDTSRC_EMBED case Patch resolves two kind of bugs, one of which is vulnerability related to KASLR. === Issue briefly === Working with FDT (via non-relocated gd::fdt_blob) from inside bootm command may lead to the reading the garbage instead of FDT nodes. And this can result in various side-effects depending on DTS nodes, being parsed during bootm. But below is my specific story how I faced with this issue due to MESON_RNG probing failure. === Bugs description === 1) Bug is revealed on: * configuration below * U-boot 2024.10 - f919c3a889f ("Prepare v2024.10") It seems, the following patch is a trigger: ea955eea4f ("fdt: automatically add /chosen/kaslr-seed if DM_RNG is enabled") Generally, CONFIG_OF_EMBED=y & CONFIG_RNG_MESON=y are the most valuable ones for reproducing the issue. ``` CONFIG_ARCH_FIXUP_FDT_MEMORY=y CONFIG_CMD_FDT=y CONFIG_DEFAULT_FDT_FILE="" CONFIG_FDT_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_OF_LIBFDT_ASSUME_MASK=0x0 CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_OF_LIBFDT=y CONFIG_OF_LIST="meson-axg-our-device-name" CONFIG_OF_REAL=y CONFIG_OF_TRANSLATE=y CONFIG_SUPPORT_OF_CONTROL=y CONFIG_SYS_FDT_PAD=0x3000 CONFIG_TOOLS_OF_LIBFDT=y CONFIG_DM_RNG=y CONFIG_RNG_MESON=y ``` 2) Due to CONFIG_OF_EMBED, the DTS is embedded into U-boot ELF and accessible via __dtb_dt_begin symbol. On early boot stage (board_f.c) the fdtdec_setup() is called only once before U-boot's relocation into top of RAM. fdtdec_setup() initializes gd::fdt_blob for FDTSRC_EMBED case: ``` gd->fdt_blob = dtb_dt_embedded(); gd->fdt_src = FDTSRC_EMBED; ``` 3) Then reloc_fdt() is called in board_f.c But due to CONFIG_OF_EMBED=y the reloc_fdt() does not update gd::fdt_blob value (strictly speaking, it is impossible for CONFIG_OF_EMBED=y, because U-boot ELF has not been relocated yet at this moment). As a result after relocation we get fdt_blob, pointing to DTS address before relocation: ``` # bdinfo <...> relocaddr = 0x000000000fedf000 reloc off = 0x000000000eedf000 <...> fdt_blob = 0x010ce6c0 << points to __dtb_dt_begin before relocation new_fdt = 0x0000000000000000 << empty erroneously fdt_size = 0x0000000000000000 << zero erroneously ``` 4) During bootm command (according to our ITS-config file) the Linux is loaded into 0x01080000 (which is very close to fdt_blob addr 0x010ce6c0). ``` ## Loading kernel from FIT Image at 04000000 ... Trying 'kernel' kernel subimage <...> Load Address: 0x01080000 ``` So Linux image overwrites the gd::fdt_blob memory location in RAM (0x010ce6c0). 5) Issue: Hence any manipulation with DTS (say, via FDT API) inside implementation of bootm command leads to accessing the fdt_blob area with garbage, that can lead to two situations: 5.1) Abort. Call to fdt_off_dt_struct() from fdt_next_tag() :: fdt_offset_ptr():: fdt_offset_ptr_() returns with garbage, that leads to tagp value being out of RAM top addr (256 Mb in our board), causing the abort: ``` Boot cmd: bootm 0x4000000#boot_evt1 bootm_run_states() <...> image_setup_libfdt() fdt_chosen() fdt_kaslrseed() uclass_get_device() uclass_get_device_tail() device_probe() device_of_to_plat() meson_rng_of_to_plat() clk_get_by_name_optional() clk_get_by_name() clk_get_by_name_nodev() ofnode_stringlist_search() fdt_stringlist_search() fdt_getprop() fdt_get_property_namelen_() fdt_first_property_offset() fdt_check_node_offset_() fdt_next_tag(): ``` tagp = fdt_offset_ptr(fdt, offset, FDT_TAGSIZE); ``` fdt_next_tag() tagp:0x22890766 fdt_next_tag() ram_top:0x10000000 (tagp OUT of RAM) "Synchronous Abort" handler, esr 0x96000010, far 0x22890766 elr: 000000000108be24 lr : 000000000108be24 (reloc) elr: 000000000ff6fe24 lr : 000000000ff6fe24 x0 : 0000000000000041 x1 : 0000000000000000 x2 : 000000000ff3b57c x3 : 0000000000000012 x4 : 000000000ded2ad5 x5 : 0000000000000020 x6 : 00000000ffffffe8 x7 : 000000000ded2f40 x8 : 00000000ffffffd8 x9 : 000000000000000d x10: 0000000000000006 x11: 000000000001869f x12: 000000000fffffff x13: 000000000fffffff x14: 0000000000000000 x15: 000000000ded2abb x16: 000000000ff3b080 x17: 0000000000000001 x18: 000000000ded3dc0 x19: 0000000022890766 x20: 00000000010cb0f0 x21: 00000000000015e4 x22: 000000000ff8f4d8 x23: 000000000000000b x24: 000000000ded2fbc x25: 000000000ffe2000 x22: 000000000ff8f4d8 x23: 000000000000000b x24: 000000000ded2fbc x25: 000000000ffe2000 x26: 000000000ffe2000 x27: 000000000000000b x28: 000000000ff9cf2d x29: 000000000ded2f40 Code: aa1603e1 91197484 52801742 94004de8 (b9400276) ``` 5.2) Vulnerability situation "KASLR is disabled". Almost the same as in (5.1), but 2 situations happen (depending on the value of garbage): * call to fdt_offset_ptr_() :: fdt_off_dt_struct(fdt) returns not so big garbage, leading to tagp, being inside RAM. * or calculations of absoffset inside fdt_offset_ptr() leads to failure of the one of if() conditions with NULL as retval. Result is fdt_next_tag() interprets the tagp as FDT_END. And we are returning from our callstack via functions' error paths, leading to "No RNG device" and "KASLR disabled due to lack of seed": ``` fdt_kaslrseed() uclass_get_device() <...> device_probe() device_of_to_plat() meson_rng_of_to_plat() clk_get_by_name() clk_get_by_name_nodev() <...> fdt_stringlist_search() fdt_getprop() fdt_get_property_namelen_() fdt_first_property_offset() fdt_check_node_offset_() fdt_next_tag(): ``` tagp = fdt_offset_ptr(fdt, offset, FDT_TAGSIZE); ``` fdt_next_tag() tagp:0000000001890677 fdt_next_tag() ram_top:0x10000000 (tagp is inside RAM) uclass_get_device_tail():486 device_probe() ret:-22 No RNG device Starting kernel ... [ 0.000000] Linux version 6.9.12 [ 0.000000] KASLR disabled due to lack of seed ``` Signed-off-by: Evgeny Bachinin --- common/board_r.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/common/board_r.c b/common/board_r.c index 62228a723e1..88dc756b2a5 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -152,6 +152,15 @@ static int initr_reloc_global_data(void) */ gd->env_addr += gd->reloc_off; #endif + + /* + * For CONFIG_OF_EMBED case the FDT is embedded into ELF, available by + * __dtb_dt_begin. After U-boot ELF self-relocation to RAM top address + * it is worth to update fdt_blob in global_data + */ + if (IS_ENABLED(CONFIG_OF_EMBED)) + gd->fdt_blob = dtb_dt_embedded(); + #ifdef CONFIG_EFI_LOADER /* * On the ARM architecture gd is mapped to a fixed register (r9 or x18). From 0bbc17f06bf3ecee019090b76c8c20480516945e Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Mon, 18 Nov 2024 21:28:00 -0600 Subject: [PATCH 40/57] configs: e850-96: Disable PSCI reset PSCI reset is not implemented in Exynos850 EL3 firmware. Disable it to fix the reset in cases where it can be used, e.g. when running EFI selftest. Signed-off-by: Sam Protsenko Signed-off-by: Minkyu Kang --- configs/e850-96_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig index 5797c6cb1f9..c36196c510c 100644 --- a/configs/e850-96_defconfig +++ b/configs/e850-96_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y +CONFIG_ARM_SMCCC=y CONFIG_ARCH_EXYNOS=y CONFIG_TEXT_BASE=0xf8800000 CONFIG_SYS_MALLOC_LEN=0x81f000 @@ -9,6 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000 CONFIG_DEFAULT_DEVICE_TREE="exynos/exynos850-e850-96" CONFIG_SYS_LOAD_ADDR=0x80000000 +# CONFIG_PSCI_RESET is not set CONFIG_ANDROID_BOOT_IMAGE=y # CONFIG_AUTOBOOT is not set # CONFIG_DISPLAY_CPUINFO is not set From ccddb0abec37f4628224ec20846b001a3e85e951 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 3 Dec 2024 11:06:10 +0100 Subject: [PATCH 41/57] power: regulator: replace some debug() by dev_dbg() Replace some debug() by dev_dbg() when dev variable is available/valid. Signed-off-by: Patrice Chotard Reviewed-by: Quentin Schulz Reviewed-by: Jaehoon Chung --- drivers/power/regulator/regulator-uclass.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index decd0802c84..80ea5e65d48 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -43,8 +44,7 @@ static void regulator_set_value_ramp_delay(struct udevice *dev, int old_uV, { int delay = DIV_ROUND_UP(abs(new_uV - old_uV), ramp_delay); - debug("regulator %s: delay %u us (%d uV -> %d uV)\n", dev->name, delay, - old_uV, new_uV); + dev_dbg(dev, "delay %u us (%d uV -> %d uV)\n", delay, old_uV, new_uV); udelay(delay); } @@ -263,7 +263,7 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp) for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; ret = uclass_find_next_device(&dev)) { if (ret) { - debug("regulator %s, ret=%d\n", dev->name, ret); + dev_dbg(dev, "ret=%d\n", ret); continue; } @@ -439,16 +439,15 @@ static int regulator_post_bind(struct udevice *dev) /* Regulator's mandatory constraint */ uc_pdata->name = dev_read_string(dev, property); if (!uc_pdata->name) { - debug("%s: dev '%s' has no property '%s'\n", - __func__, dev->name, property); + dev_dbg(dev, "has no property '%s'\n", property); uc_pdata->name = dev_read_name(dev); if (!uc_pdata->name) return -EINVAL; } if (!regulator_name_is_unique(dev, uc_pdata->name)) { - debug("'%s' of dev: '%s', has nonunique value: '%s\n", - property, dev->name, uc_pdata->name); + dev_dbg(dev, "'%s' has nonunique value: '%s\n", + property, uc_pdata->name); return -EINVAL; } From 74cd1af1124fbe3cd16c58bc3ad9ff1f9c6ecf3e Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 3 Dec 2024 11:06:11 +0100 Subject: [PATCH 42/57] power: regulator: replace dev_dbg() by dev_err() in regulator_post_bind() To ease debugging, use dev_err() instead of dev_dbg() for alerting when regulator has nonunique value. Signed-off-by: Patrice Chotard Reviewed-by: Quentin Schulz Reviewed-by: Jaehoon Chung --- drivers/power/regulator/regulator-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 80ea5e65d48..09567eb9dbb 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -446,7 +446,7 @@ static int regulator_post_bind(struct udevice *dev) } if (!regulator_name_is_unique(dev, uc_pdata->name)) { - dev_dbg(dev, "'%s' has nonunique value: '%s\n", + dev_err(dev, "'%s' has nonunique value: '%s\n", property, uc_pdata->name); return -EINVAL; } From 05396fb724551e57ccf6de15ce9f4c0e3128f82c Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Tue, 3 Dec 2024 18:13:37 +0200 Subject: [PATCH 43/57] efi_loader: Check for a valid fw_name before auto generating GUIDs The gen_v5_guid() is a void and does no error checking with pointers being available etc. Instead it expects all things to be in place to generate GUIDs. If a board capsule definition is buggy and does not define the firmware names when enabling capsule updates, the board will crash trying to bring up the EFI subsystem. Check for a valid firmware name before generating GUIDs. Reviewed-by: Heinrich Schuchardt Signed-off-by: Ilias Apalodimas --- lib/efi_loader/efi_firmware.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c index 6650c2b8071..112775daf4c 100644 --- a/lib/efi_loader/efi_firmware.c +++ b/lib/efi_loader/efi_firmware.c @@ -281,6 +281,10 @@ static efi_status_t efi_gen_capsule_guids(void) } for (i = 0; i < update_info.num_images; i++) { + if (!fw_array[i].fw_name) { + log_err("fw_name is not defined. Not generating capsule GUIDs\n"); + return EFI_INVALID_PARAMETER; + } gen_v5_guid(&namespace, &fw_array[i].image_type_id, compatible, strlen(compatible), From 1d9aa4a283daa1e609130b5457c9857d62f1d1cb Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Mon, 2 Dec 2024 16:42:45 +0200 Subject: [PATCH 44/57] lmb: Fix the allocation of overlapping memory areas with !LMB_NONE At the moment the LMB allocator will return 'success' immediately on two consecutive allocations if the second one is smaller and the flags match without resizing the reserved area. This is problematic for two reasons, first of all the new updated allocation won't update the size and we end up holding more memory than needed, but most importantly it breaks the EFI SCT tests since EFI now allocates via LMB. More specifically when EFI requests a specific address twice with the EFI_ALLOCATE_ADDRESS flag set, the first allocation will succeed and update the EFI memory map. Due to the LMB behavior the second allocation will also succeed but the address ranges are already in the EFI memory map due the first allocation. EFI will then fail to update the memory map, returning EFI_OUT_OF_RESOURCES instead of EFI_NOT_FOUND which break EFI conformance. So let's remove the fast check with is problematic anyway and leave LMB resize and calculate address properly. LMB will now - try to resize the reservations for LMB_NONE - return -1 if the memory is not LMB_NONE and already reserved The LMB code needs some cleanup in that part, but since we are close to 2025.01 do the easy fix and plan to refactor it later. Also update the dm tests with the new behavior. Fixes: commit 22f2c9ed9f53 ("efi: memory: use the lmb API's for allocating and freeing memory") Signed-off-by: Ilias Apalodimas --- lib/lmb.c | 9 --------- test/lib/lmb.c | 22 +++++++++++++++++++++- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/lib/lmb.c b/lib/lmb.c index 14b9b8466ff..3a765c11bee 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -201,15 +201,6 @@ static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base, phys_addr_t rgnbase = rgn[i].base; phys_size_t rgnsize = rgn[i].size; phys_size_t rgnflags = rgn[i].flags; - phys_addr_t end = base + size - 1; - phys_addr_t rgnend = rgnbase + rgnsize - 1; - if (rgnbase <= base && end <= rgnend) { - if (flags == rgnflags) - /* Already have this region, so we're done */ - return 0; - else - return -1; /* regions with new flags */ - } ret = lmb_addrs_adjacent(base, size, rgnbase, rgnsize); if (ret > 0) { diff --git a/test/lib/lmb.c b/test/lib/lmb.c index c917115b7b6..0bd29e2a4fe 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -529,6 +529,26 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ret = lmb_add(ram, ram_size); ut_asserteq(ret, 0); + /* Try to allocate a page twice */ + b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NONE); + ut_asserteq(b, alloc_addr_a); + b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); + ut_asserteq(b, 0); + b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NONE); + ut_asserteq(b, alloc_addr_a); + b = lmb_alloc_addr_flags(alloc_addr_a, 0x2000, LMB_NONE); + ut_asserteq(b, alloc_addr_a); + ret = lmb_free(alloc_addr_a, 0x2000); + ut_asserteq(ret, 0); + b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); + ut_asserteq(b, alloc_addr_a); + b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NONE); + ut_asserteq(b, 0); + b = lmb_alloc_addr_flags(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); + ut_asserteq(b, 0); + ret = lmb_free(alloc_addr_a, 0x1000); + ut_asserteq(ret, 0); + /* reserve 3 blocks */ ret = lmb_reserve(alloc_addr_a, 0x10000); ut_asserteq(ret, 0); @@ -734,7 +754,7 @@ static int lib_test_lmb_flags(struct unit_test_state *uts) /* reserve again, same flag */ ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NOMAP); - ut_asserteq(ret, 0); + ut_asserteq(ret, -1L); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000, 0, 0, 0, 0); From ef9574da96f0cb8644c2a211000447cbf625260f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 6 Dec 2024 17:40:50 -0600 Subject: [PATCH 45/57] configs: Resync with savedefconfig Resync all defconfig files using qconfig.py Signed-off-by: Tom Rini --- configs/bcm947622_defconfig | 3 --- configs/bcm94912_defconfig | 3 --- configs/bcm963146_defconfig | 3 --- configs/bcm963158_defconfig | 3 --- configs/bcm963178_defconfig | 3 --- configs/bcm96756_defconfig | 3 --- configs/bcm96813_defconfig | 3 --- configs/bcm96855_defconfig | 3 --- configs/bcm96856_defconfig | 3 --- configs/bcm96858_defconfig | 3 --- configs/bcm96878_defconfig | 3 --- configs/sifive_unmatched_defconfig | 2 +- configs/starfive_visionfive2_defconfig | 3 --- 13 files changed, 1 insertion(+), 37 deletions(-) diff --git a/configs/bcm947622_defconfig b/configs/bcm947622_defconfig index cf0651c6502..566f9f2920f 100644 --- a/configs/bcm947622_defconfig +++ b/configs/bcm947622_defconfig @@ -18,10 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y -CONFIG_DM=y CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/bcm94912_defconfig b/configs/bcm94912_defconfig index bce823b9041..46bbfb67980 100644 --- a/configs/bcm94912_defconfig +++ b/configs/bcm94912_defconfig @@ -18,10 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y -CONFIG_DM=y CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/bcm963146_defconfig b/configs/bcm963146_defconfig index 691d055e310..239a8a10fa5 100644 --- a/configs/bcm963146_defconfig +++ b/configs/bcm963146_defconfig @@ -18,10 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y -CONFIG_DM=y CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/bcm963158_defconfig b/configs/bcm963158_defconfig index 6e4a85ec3a3..a6cfea6cd79 100644 --- a/configs/bcm963158_defconfig +++ b/configs/bcm963158_defconfig @@ -18,10 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y -CONFIG_DM=y CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/bcm963178_defconfig b/configs/bcm963178_defconfig index 60a198719a3..95c9c8e396e 100644 --- a/configs/bcm963178_defconfig +++ b/configs/bcm963178_defconfig @@ -19,10 +19,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y -CONFIG_DM=y CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/bcm96756_defconfig b/configs/bcm96756_defconfig index 4b1fa991a04..bfd309c25f5 100644 --- a/configs/bcm96756_defconfig +++ b/configs/bcm96756_defconfig @@ -19,10 +19,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y -CONFIG_DM=y CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/bcm96813_defconfig b/configs/bcm96813_defconfig index 553bdc148b2..7f165231648 100644 --- a/configs/bcm96813_defconfig +++ b/configs/bcm96813_defconfig @@ -18,10 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y -CONFIG_DM=y CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/bcm96855_defconfig b/configs/bcm96855_defconfig index ff6dff0fca6..342be0a0e17 100644 --- a/configs/bcm96855_defconfig +++ b/configs/bcm96855_defconfig @@ -19,10 +19,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y -CONFIG_DM=y CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/bcm96856_defconfig b/configs/bcm96856_defconfig index 7c6fba29abf..5f22186966f 100644 --- a/configs/bcm96856_defconfig +++ b/configs/bcm96856_defconfig @@ -18,10 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y -CONFIG_DM=y CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/bcm96858_defconfig b/configs/bcm96858_defconfig index 3e11b401260..682cb14e898 100644 --- a/configs/bcm96858_defconfig +++ b/configs/bcm96858_defconfig @@ -18,10 +18,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y -CONFIG_DM=y CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/bcm96878_defconfig b/configs/bcm96878_defconfig index 52c869aab9b..ad65187c30c 100644 --- a/configs/bcm96878_defconfig +++ b/configs/bcm96878_defconfig @@ -19,10 +19,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y -CONFIG_OF_CONTROL=y -CONFIG_OF_UPSTREAM=y CONFIG_OF_EMBED=y -CONFIG_DM=y CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 6f511796a20..4fed7eda948 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -36,7 +36,6 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ID_EEPROM=y CONFIG_PCI_INIT_R=y -CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_SPL_MAX_SIZE=0x100000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y @@ -60,6 +59,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x54 CONFIG_SPI_FLASH_ISSI=y CONFIG_E1000=y CONFIG_NVME_PCI=y +CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCIE_DW_SIFIVE=y CONFIG_SCSI=y CONFIG_USB=y diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 319e1d358a0..20f89ae6796 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -56,9 +56,6 @@ CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000 -CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2 CONFIG_SPL_SYS_MALLOC_SIZE=0x400000 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y From 1a48b0be93d48f9ec5498297ec775fb572d3d150 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Mon, 2 Dec 2024 12:36:24 +0530 Subject: [PATCH 46/57] lmb: prohibit allocations above ram_top even from same bank There are platforms which set the value of ram_top based on certain restrictions that the platform might have in accessing memory above ram_top, even when the memory region is in the same DRAM bank. So, even though the LMB allocator works as expected, when trying to allocate memory above ram_top, prohibit this by marking all memory above ram_top as reserved, even if the said memory region is from the same bank. Signed-off-by: Sughosh Ganu Tested-by: Andreas Schwab --- lib/lmb.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/lib/lmb.c b/lib/lmb.c index 3a765c11bee..b03237bc06c 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -606,6 +606,7 @@ static __maybe_unused void lmb_reserve_common_spl(void) void lmb_add_memory(void) { int i; + phys_addr_t bank_end; phys_size_t size; u64 ram_top = gd->ram_top; struct bd_info *bd = gd->bd; @@ -619,6 +620,8 @@ void lmb_add_memory(void) for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { size = bd->bi_dram[i].size; + bank_end = bd->bi_dram[i].start + size; + if (size) { lmb_add(bd->bi_dram[i].start, size); @@ -630,6 +633,9 @@ void lmb_add_memory(void) if (bd->bi_dram[i].start >= ram_top) lmb_reserve_flags(bd->bi_dram[i].start, size, LMB_NOOVERWRITE); + else if (bank_end > ram_top) + lmb_reserve_flags(ram_top, bank_end - ram_top, + LMB_NOOVERWRITE); } } } From 1ac28383502e40113b56b7a124b9b9200167f649 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 5 Dec 2024 21:36:19 +0100 Subject: [PATCH 47/57] rtc: CONFIGS_RTC_PL031 must depend on CONFIGS_DM_RTC Building qemu_arm64_defconfig with CONFIGS_DM_RTC=n and CONFIGS_RTC_PL031=y leads to a build failure. Adjust the vexpress64 configuration to avoid circular dependency. Signed-off-by: Heinrich Schuchardt --- board/armltd/vexpress64/Kconfig | 2 +- drivers/rtc/Kconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index cf998096e45..584b5455e97 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -16,8 +16,8 @@ config VEXPRESS64_BASE_MODEL select VIRTIO_BLK if VIRTIO_MMIO select VIRTIO_NET if VIRTIO_MMIO select DM_ETH if VIRTIO_NET + imply DM_RTC imply RTC_PL031 - select DM_RTC if RTC_PL031 imply EFI_SET_TIME if DM_RTC select LINUX_KERNEL_IMAGE_HEADER select POSITION_INDEPENDENT diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 7fc53a6d61e..9c2d1398247 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -203,6 +203,7 @@ config RTC_RX8025 config RTC_PL031 bool "Enable ARM AMBA PL031 RTC driver" + depends on DM_RTC help The ARM PrimeCell Real Time Clock (PL031) is an optional SoC peripheral based on the Advanced Microcontroller Bus Architecture From c7401fc1d99b88a3a3d16519f07974473908cd46 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 6 Dec 2024 12:37:09 +0100 Subject: [PATCH 48/57] net: disable MBEDTLS in SPL Building SPL fails with MBEDTLS enabled. Currently we don't need it there. Signed-off-by: Heinrich Schuchardt Acked-by: Jerome Forissier --- include/u-boot/md5.h | 6 ++++-- include/u-boot/sha1.h | 5 +++-- include/u-boot/sha256.h | 5 +++-- include/u-boot/sha512.h | 5 +++-- lib/Makefile | 2 +- lib/lwip/Makefile | 2 +- lib/lwip/u-boot/lwipopts.h | 4 +++- lib/md5.c | 6 ++++-- lib/sha1.c | 6 ++++-- lib/sha256.c | 6 ++++-- lib/sha512.c | 12 ++++++++---- 11 files changed, 38 insertions(+), 21 deletions(-) diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h index c98b1a58088..2a52e169051 100644 --- a/include/u-boot/md5.h +++ b/include/u-boot/md5.h @@ -6,7 +6,9 @@ #ifndef _MD5_H #define _MD5_H -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#include + +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) #include #endif #include "compiler.h" @@ -14,7 +16,7 @@ #define MD5_SUM_LEN 16 #define MD5_DEF_CHUNK_SZ 0x10000 -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) typedef mbedtls_md5_context MD5Context; #else typedef struct MD5Context { diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h index 2fca7f1be16..dd66258bbe9 100644 --- a/include/u-boot/sha1.h +++ b/include/u-boot/sha1.h @@ -14,9 +14,10 @@ #ifndef _SHA1_H #define _SHA1_H +#include #include -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) /* * FIXME: * MbedTLS define the members of "mbedtls_sha256_context" as private, @@ -47,7 +48,7 @@ extern "C" { extern const uint8_t sha1_der_prefix[]; -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) typedef mbedtls_sha1_context sha1_context; #else /** diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h index b58d5b58d39..44a9b528b48 100644 --- a/include/u-boot/sha256.h +++ b/include/u-boot/sha256.h @@ -1,9 +1,10 @@ #ifndef _SHA256_H #define _SHA256_H +#include #include -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) /* * FIXME: * MbedTLS define the members of "mbedtls_sha256_context" as private, @@ -27,7 +28,7 @@ extern const uint8_t sha256_der_prefix[]; /* Reset watchdog each time we process this many bytes */ #define CHUNKSZ_SHA256 (64 * 1024) -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) typedef mbedtls_sha256_context sha256_context; #else typedef struct { diff --git a/include/u-boot/sha512.h b/include/u-boot/sha512.h index 7e10f590a1d..92660d93357 100644 --- a/include/u-boot/sha512.h +++ b/include/u-boot/sha512.h @@ -1,9 +1,10 @@ #ifndef _SHA512_H #define _SHA512_H +#include #include -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) #include #endif @@ -16,7 +17,7 @@ #define CHUNKSZ_SHA384 (16 * 1024) #define CHUNKSZ_SHA512 (16 * 1024) -#if defined(CONFIG_MBEDTLS_LIB_CRYPTO) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_CRYPTO) typedef mbedtls_sha512_context sha384_context; typedef mbedtls_sha512_context sha512_context; #else diff --git a/lib/Makefile b/lib/Makefile index dbcfa87ebd6..d24ed629732 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -97,7 +97,7 @@ obj-$(CONFIG_LIBAVB) += libavb/ obj-$(CONFIG_$(PHASE_)OF_LIBFDT) += libfdt/ obj-$(CONFIG_$(PHASE_)OF_REAL) += fdtdec_common.o fdtdec.o -obj-$(CONFIG_MBEDTLS_LIB) += mbedtls/ +obj-$(CONFIG_$(XPL_)MBEDTLS_LIB) += mbedtls/ obj-$(CONFIG_NET_LWIP) += lwip/ diff --git a/lib/lwip/Makefile b/lib/lwip/Makefile index 19e5c6897f5..fe2b64c9acc 100644 --- a/lib/lwip/Makefile +++ b/lib/lwip/Makefile @@ -54,5 +54,5 @@ obj-y += \ lwip/src/core/udp.o \ lwip/src/netif/ethernet.o -obj-$(CONFIG_MBEDTLS_LIB_TLS) += lwip/src/apps/altcp_tls/altcp_tls_mbedtls.o \ +obj-$(CONFIG_$(XPL_)MBEDTLS_LIB_TLS) += lwip/src/apps/altcp_tls/altcp_tls_mbedtls.o \ lwip/src/apps/altcp_tls/altcp_tls_mbedtls_mem.o diff --git a/lib/lwip/u-boot/lwipopts.h b/lib/lwip/u-boot/lwipopts.h index 88d6faf327a..edac74ff7a2 100644 --- a/lib/lwip/u-boot/lwipopts.h +++ b/lib/lwip/u-boot/lwipopts.h @@ -5,6 +5,8 @@ #ifndef LWIP_UBOOT_LWIPOPTS_H #define LWIP_UBOOT_LWIPOPTS_H +#include + #if defined(CONFIG_LWIP_DEBUG) #define LWIP_DEBUG 1 #define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL @@ -154,7 +156,7 @@ #define MEMP_MEM_INIT 1 #define MEM_LIBC_MALLOC 1 -#if defined(CONFIG_MBEDTLS_LIB_TLS) +#if CONFIG_IS_ENABLED(MBEDTLS_LIB_TLS) #define LWIP_ALTCP 1 #define LWIP_ALTCP_TLS 1 #define LWIP_ALTCP_TLS_MBEDTLS 1 diff --git a/lib/md5.c b/lib/md5.c index 2d8977b2e85..e3eab8a9149 100644 --- a/lib/md5.c +++ b/lib/md5.c @@ -272,14 +272,16 @@ md5_wd(const unsigned char *input, unsigned int len, unsigned char output[16], unsigned int chunk_sz) { MD5Context context; -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) const unsigned char *end, *curr; int chunk; #endif MD5Init(&context); -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) curr = input; end = input + len; while (curr < end) { diff --git a/lib/sha1.c b/lib/sha1.c index a9d6497c4ce..be502c6126b 100644 --- a/lib/sha1.c +++ b/lib/sha1.c @@ -312,14 +312,16 @@ void sha1_csum_wd(const unsigned char *input, unsigned int ilen, unsigned char *output, unsigned int chunk_sz) { sha1_context ctx; -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) const unsigned char *end, *curr; int chunk; #endif sha1_starts (&ctx); -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) curr = input; end = input + ilen; while (curr < end) { diff --git a/lib/sha256.c b/lib/sha256.c index 329802fd827..fb195d988f1 100644 --- a/lib/sha256.c +++ b/lib/sha256.c @@ -273,7 +273,8 @@ void sha256_csum_wd(const unsigned char *input, unsigned int ilen, unsigned char *output, unsigned int chunk_sz) { sha256_context ctx; -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) const unsigned char *end; unsigned char *curr; int chunk; @@ -281,7 +282,8 @@ void sha256_csum_wd(const unsigned char *input, unsigned int ilen, sha256_starts(&ctx); -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) curr = (unsigned char *)input; end = input + ilen; while (curr < end) { diff --git a/lib/sha512.c b/lib/sha512.c index ea555ff33eb..0e75c1a943b 100644 --- a/lib/sha512.c +++ b/lib/sha512.c @@ -288,7 +288,8 @@ void sha384_csum_wd(const unsigned char *input, unsigned int ilen, unsigned char *output, unsigned int chunk_sz) { sha512_context ctx; -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) const unsigned char *end; unsigned char *curr; int chunk; @@ -296,7 +297,8 @@ void sha384_csum_wd(const unsigned char *input, unsigned int ilen, sha384_starts(&ctx); -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) curr = (unsigned char *)input; end = input + ilen; while (curr < end) { @@ -351,7 +353,8 @@ void sha512_csum_wd(const unsigned char *input, unsigned int ilen, unsigned char *output, unsigned int chunk_sz) { sha512_context ctx; -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) const unsigned char *end; unsigned char *curr; int chunk; @@ -359,7 +362,8 @@ void sha512_csum_wd(const unsigned char *input, unsigned int ilen, sha512_starts(&ctx); -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#if !defined(USE_HOSTCC) && \ + (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) curr = (unsigned char *)input; end = input + ilen; while (curr < end) { From 1f40dbad60d0a35291f7f43527a6facc82ea1e72 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Vincent=20Stehl=C3=A9?= Date: Fri, 6 Dec 2024 08:58:53 +0100 Subject: [PATCH 49/57] arm: qemu: fix update_info declaration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a missing comma in the update_info structure declaration. This fixes the following build error when building with EFI_RUNTIME_UPDATE_CAPSULE or EFI_CAPSULE_ON_DISK: board/emulation/qemu-arm/qemu-arm.c:52:9: error: request for member ‘images’ in something not a structure or union Fixes: cccea18813c4 ("efi_loader: add the number of image entries in efi_capsule_update_info") Signed-off-by: Vincent Stehlé Cc: Masahisa Kojima Cc: Tuomas Tynkkynen Cc: Tom Rini --- board/emulation/qemu-arm/qemu-arm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index 6095cb02b23..e0e18b4dfea 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -48,7 +48,7 @@ struct efi_fw_image fw_images[] = { }; struct efi_capsule_update_info update_info = { - .num_images = ARRAY_SIZE(fw_images) + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; From 45f05f681224d88d1b170063001b59edc8fc24cf Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 6 Dec 2024 12:56:45 +0200 Subject: [PATCH 50/57] mbedtls: remove MBEDTLS_HAVE_TIME When MbedTLS TLS features were added MBEDTLS_HAVE_TIME was defined as part of enabling https:// support. However that pointed to the wrong function which could crash if it received a NULL pointer. Looking closer that function is not really needed, as it only seems to increase the RNG entropy by using 4b of the current time and date. The reason that was enabled is that lwIP was unconditionally requiring it, although it's configurable and can be turned off. Since lwIP doesn't use that field anywhere else, make it conditional and disable it from our config. Fixes: commit a564f5094f62 ("mbedtls: Enable TLS 1.2 support") Reported-by: Heinrich Schuchardt Signed-off-by: Ilias Apalodimas Reviewed-by: Heinrich Schuchardt Acked-by: Jerome Forissier --- lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c | 2 ++ lib/mbedtls/mbedtls_def_config.h | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c b/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c index 6643b05ee94..46421588fef 100644 --- a/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c +++ b/lib/lwip/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c @@ -692,7 +692,9 @@ altcp_tls_set_session(struct altcp_pcb *conn, struct altcp_tls_session *session) if (session && conn && conn->state) { altcp_mbedtls_state_t *state = (altcp_mbedtls_state_t *)conn->state; int ret = -1; +#ifdef MBEDTLS_HAVE_TIME if (session->data.MBEDTLS_PRIVATE(start)) +#endif ret = mbedtls_ssl_set_session(&state->ssl_context, &session->data); return ret < 0 ? ERR_VAL : ERR_OK; } diff --git a/lib/mbedtls/mbedtls_def_config.h b/lib/mbedtls/mbedtls_def_config.h index d27f017d084..1d2314e90e4 100644 --- a/lib/mbedtls/mbedtls_def_config.h +++ b/lib/mbedtls/mbedtls_def_config.h @@ -92,9 +92,6 @@ /* Generic options */ #define MBEDTLS_ENTROPY_HARDWARE_ALT -#define MBEDTLS_HAVE_TIME -#define MBEDTLS_PLATFORM_MS_TIME_ALT -#define MBEDTLS_PLATFORM_TIME_MACRO rtc_mktime #define MBEDTLS_PLATFORM_C #define MBEDTLS_SSL_CLI_C #define MBEDTLS_SSL_TLS_C From 9a699a0a0d62b326d04ac248578b6ce6f53be525 Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Tue, 19 Nov 2024 19:36:26 +0000 Subject: [PATCH 51/57] clk: rzg2l: Ignore enable for core clocks In the RZ/G2L family, core clocks are always on and can't be disabled. However, drivers which are shared with other SoCs may call clk_enable() or clk_enable_bulk() for a clock referenced in the device tree which happens to be a core clock on the RZ/G2L. To avoid the need for conditionals in these drivers, simply ignore attempts to enable a core clock. Signed-off-by: Paul Barker Reviewed-by: Marek Vasut --- drivers/clk/renesas/rzg2l-cpg.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index c8735d869cf..3c5340df8ee 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -69,7 +69,15 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable) dev_dbg(clk->dev, "%s %s clock %u\n", enable ? "enable" : "disable", is_mod_clk(clk->id) ? "module" : "core", cpg_clk_id); + if (!is_mod_clk(clk->id)) { + /* + * Non-module clocks are always on. Ignore attempts to enable + * them and reject attempts to disable them. + */ + if (enable) + return 0; + dev_err(clk->dev, "ID %lu is not a module clock\n", clk->id); return -EINVAL; } From 2b1a5efca8891ea320c23acd3681ca8bdb7fd15b Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Wed, 20 Nov 2024 09:49:39 +0000 Subject: [PATCH 52/57] net: ravb: Simplify max-speed handling in ravb_of_to_plat We can call dev_read_u32_default() instead of calling fdt_getprop() then fdt32_to_cpu(). Signed-off-by: Paul Barker Reviewed-by: Marek Vasut --- drivers/net/ravb.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index f1401d2f6ed..231764e60b5 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -649,7 +649,6 @@ static const struct eth_ops ravb_ops = { int ravb_of_to_plat(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); - const fdt32_t *cell; pdata->iobase = dev_read_addr(dev); @@ -657,10 +656,7 @@ int ravb_of_to_plat(struct udevice *dev) if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) return -EINVAL; - pdata->max_speed = 1000; - cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); - if (cell) - pdata->max_speed = fdt32_to_cpu(*cell); + pdata->max_speed = dev_read_u32_default(dev, "max-speed", 1000); sprintf(bb_miiphy_buses[0].name, dev->name); From 215663f5e47db92c6c13107e877a943c3e70aa2a Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Wed, 20 Nov 2024 09:48:28 +0000 Subject: [PATCH 53/57] pinctrl: rzg2l: Support 2.5V PVDD for Ethernet interfaces The Ethenet interfaces on the Renesas RZ/G2L SoC family can operate at multiple power supply voltages: 3.3V (default value), 2.5V and 1.8V. rzg2l_pinconf_set() is extended to support the 2.5V setting, with a check to ensure this is only used on Ethernet interfaces as it is not supported on the SD & QSPI interfaces. While we're modifying rzg2l_pinconf_set(), drop the unnecessary default value for pwr_reg as it is set in every branch of the following if condition. Signed-off-by: Paul Barker Reviewed-by: Marek Vasut --- drivers/pinctrl/renesas/rzg2l-pfc.c | 49 ++++++++++++++++++++--------- include/renesas/rzg2l-pfc.h | 2 ++ 2 files changed, 37 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c b/drivers/pinctrl/renesas/rzg2l-pfc.c index e88ec1c1837..0098e2d52d5 100644 --- a/drivers/pinctrl/renesas/rzg2l-pfc.c +++ b/drivers/pinctrl/renesas/rzg2l-pfc.c @@ -394,18 +394,10 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector, } case PIN_CONFIG_POWER_SOURCE: { - u32 pwr_reg = 0x0; + bool support_2500 = false; + u32 pwr_reg; + u32 value; - /* argument is in mV */ - if (argument != 1800 && argument != 3300) { - dev_err(dev, "Invalid mV %u\n", argument); - return -EINVAL; - } - - /* - * TODO: PIN_CFG_IO_VMC_ETH0 & PIN_CFG_IO_VMC_ETH1 will be - * handled when the RZ/G2L Ethernet driver is added. - */ if (cfg & PIN_CFG_IO_VMC_SD0) { dev_dbg(dev, "port off %u:%u set SD_CH 0 PVDD=%u\n", port_offset, pin, argument); @@ -418,13 +410,42 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector, dev_dbg(dev, "port off %u:%u set QSPI PVDD=%u\n", port_offset, pin, argument); pwr_reg = QSPI; + } else if (cfg & PIN_CFG_IO_VMC_ETH0) { + dev_dbg(dev, "port off %u:%u set ETH0 PVDD=%u\n", + port_offset, pin, argument); + pwr_reg = ETH_POC(0); + support_2500 = true; + } else if (cfg & PIN_CFG_IO_VMC_ETH1) { + dev_dbg(dev, "port off %u:%u set ETH1 PVDD=%u\n", + port_offset, pin, argument); + pwr_reg = ETH_POC(1); + support_2500 = true; } else { - dev_dbg(dev, "pin power source is not selectable\n"); + dev_dbg(dev, "port off %u:%u PVDD is not selectable\n", + port_offset, pin); return -EINVAL; } - writel((argument == 1800) ? PVDD_1800 : PVDD_3300, - data->base + pwr_reg); + /* argument is in mV */ + switch (argument) { + case 1800: + value = PVDD_1800; + break; + case 3300: + value = PVDD_3300; + break; + case 2500: + if (support_2500) { + value = PVDD_2500; + break; + } + fallthrough; + default: + dev_err(dev, "Invalid mV %u\n", argument); + return -EINVAL; + } + + writel(value, data->base + pwr_reg); break; } diff --git a/include/renesas/rzg2l-pfc.h b/include/renesas/rzg2l-pfc.h index 2df17ece2a3..d1015b1d2ac 100644 --- a/include/renesas/rzg2l-pfc.h +++ b/include/renesas/rzg2l-pfc.h @@ -77,9 +77,11 @@ #define IEN(n) (0x1800 + (n) * 8) #define PWPR 0x3014 #define SD_CH(n) (0x3000 + (n) * 4) +#define ETH_POC(ch) (0x300c + (ch) * 4) #define QSPI 0x3008 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ +#define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ #define PWPR_B0WI BIT(7) /* Bit Write Disable */ From bba516a772853595901a7359209bc588d2bffda0 Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Wed, 20 Nov 2024 09:48:29 +0000 Subject: [PATCH 54/57] pinctrl: rzg2l: Support Ethernet TXC output enable On the RZ/G2L SoC family, the direction of the Ethernet TXC/TX_CLK signal is selectable to support an Ethernet PHY operating in either MII or RGMII mode. By default, the signal is configured as an input and MII mode is supported. The ETH_MODE register can be modified to configure this signal as an output to support RGMII mode. As this signal is be default an input, and can optionally be switched to an output, it maps neatly onto an `output-enable` property in the device tree. Signed-off-by: Paul Barker Reviewed-by: Marek Vasut --- drivers/pinctrl/renesas/rzg2l-pfc.c | 31 +++++++++++++++++++++++++++-- include/renesas/rzg2l-pfc.h | 2 ++ 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c b/drivers/pinctrl/renesas/rzg2l-pfc.c index 0098e2d52d5..af371bd0ff1 100644 --- a/drivers/pinctrl/renesas/rzg2l-pfc.c +++ b/drivers/pinctrl/renesas/rzg2l-pfc.c @@ -180,7 +180,7 @@ static const u32 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), - RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), @@ -189,7 +189,7 @@ static const u32 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), - RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), @@ -449,6 +449,32 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector, break; } + case PIN_CONFIG_OUTPUT_ENABLE: { + u8 ch; + + if (!(cfg & PIN_CFG_OEN)) { + dev_err(dev, "pin does not support OEN\n"); + return -EINVAL; + } + + /* + * We can determine which Ethernet interface we're dealing with from + * the caps. + */ + if (cfg & PIN_CFG_IO_VMC_ETH0) + ch = 0; + else /* PIN_CFG_IO_VMC_ETH1 */ + ch = 1; + + dev_dbg(dev, "set ETH%u TXC OEN=%u\n", ch, argument); + if (argument) + clrbits_8(data->base + ETH_MODE, BIT(ch)); + else + setbits_8(data->base + ETH_MODE, BIT(ch)); + + break; + } + default: dev_err(dev, "Invalid pinconf parameter\n"); return -EOPNOTSUPP; @@ -542,6 +568,7 @@ static int rzg2l_get_pin_muxing(struct udevice *dev, unsigned int selector, static const struct pinconf_param rzg2l_pinconf_params[] = { { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 }, { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 /* mV */ }, }; diff --git a/include/renesas/rzg2l-pfc.h b/include/renesas/rzg2l-pfc.h index d1015b1d2ac..0c94487754d 100644 --- a/include/renesas/rzg2l-pfc.h +++ b/include/renesas/rzg2l-pfc.h @@ -22,6 +22,7 @@ #define PIN_CFG_FILONOFF BIT(10) #define PIN_CFG_FILNUM BIT(11) #define PIN_CFG_FILCLKSEL BIT(12) +#define PIN_CFG_OEN BIT(13) #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ PIN_CFG_SR | \ @@ -79,6 +80,7 @@ #define SD_CH(n) (0x3000 + (n) * 4) #define ETH_POC(ch) (0x300c + (ch) * 4) #define QSPI 0x3008 +#define ETH_MODE 0x3018 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ #define PVDD_2500 2 /* I/O domain voltage 2.5V */ From 3a735cff5f2ec4d426e27d57da835a075388464c Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Wed, 20 Nov 2024 09:48:30 +0000 Subject: [PATCH 55/57] pinctrl: rzg2l: Drop unnecessary scope In rzg2l_pinconf_set(), there are no new variables defined in the case statement for PIN_CONFIG_INPUT_ENABLE so no additional scope is needed. Signed-off-by: Paul Barker Reviewed-by: Marek Vasut --- drivers/pinctrl/renesas/rzg2l-pfc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c b/drivers/pinctrl/renesas/rzg2l-pfc.c index af371bd0ff1..3c751e9473a 100644 --- a/drivers/pinctrl/renesas/rzg2l-pfc.c +++ b/drivers/pinctrl/renesas/rzg2l-pfc.c @@ -381,7 +381,7 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector, } switch (param) { - case PIN_CONFIG_INPUT_ENABLE: { + case PIN_CONFIG_INPUT_ENABLE: if (!(cfg & PIN_CFG_IEN)) { dev_err(dev, "pin does not support IEN\n"); return -EINVAL; @@ -391,7 +391,6 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector, port_offset, pin, argument); rzg2l_rmw_pin_config(data, IEN(port_offset), pin, IEN_MASK, !!argument); break; - } case PIN_CONFIG_POWER_SOURCE: { bool support_2500 = false; From 455e66bc598935c01621e77709866eb54a6fbd5f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 28 Nov 2024 05:11:19 +0100 Subject: [PATCH 56/57] arm64: renesas: Disable AVB1 and AVB2 on R8A779G0 V4H White Hawk board The U-Boot is currently not capable of handling ethernet-phy-ieee802.3-c45 PHYs correctly, and also does not handle MDIO bus wide reset-gpios property. Until proper C45 PHY support lands in U-Boot, disable AVB1/AVB2 interfaces. This only disables the two MACs with 88Q2110/88Q2112 100/1000BASE-T1 PHYs on ethenet sub-board, the main board AVB0 ethernet is unaffected. Signed-off-by: Marek Vasut --- arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi index c3704d789e8..531767cfdb2 100644 --- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi @@ -13,6 +13,14 @@ }; }; +&avb1 { + status = "disabled"; +}; + +&avb2 { + status = "disabled"; +}; + &rpc { flash@0 { spi-tx-bus-width = <1>; From b841e559cd26ffcb20f22e8ee75debed9616c002 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 9 Dec 2024 16:09:28 -0600 Subject: [PATCH 57/57] Prepare v2025.01-rc4 Signed-off-by: Tom Rini --- Makefile | 2 +- doc/develop/release_cycle.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 7933ade6eff..2e49f6088cc 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2025 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc3 +EXTRAVERSION = -rc4 NAME = # *DOCUMENTATION* diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index c742c2f8e20..9f9252b18d2 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -73,7 +73,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2025.01-rc3 was released on Mon 25 November 2024. -.. * U-Boot v2025.01-rc4 was released on Mon 09 December 2024. +* U-Boot v2025.01-rc4 was released on Mon 09 December 2024. .. * U-Boot v2025.01-rc5 was released on Mon 23 December 2024.