Prepare v2025.01-rc3

-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmdFAVQACgkQFHw5/5Y0
 tyyyfQwAuHAoOJ2Q5KnesduF9tkzeSRoziCNig3D+VItbJSxKqnBxPB9U+AxxsZ8
 JVA1e5qSwcblqybyWHrFUVTYVlI4j9oJIOTQKtEmUnDUNY+vd5eT9+V8kmQqnbU0
 mhE8fuH6wSHQ3K+tdVSJuWxcZJfFOE5dZKAxz0z/LysqNfJ/r/iqg2l0YYozId2s
 Kyyq7K25jNilcWAw4zUbGcdvM+H53KNzQ3WcZ36HwenlXWoQJOKCbEEskYxAaa0e
 hSEAQCNeuD1oVoZH1jc9dP6htLx5gmOaSbIScwfaOMqBQHyWQTjv/sMEy8wGSMdA
 PqDGClxU0GCenhbS6waY9GPMLYV0JtyXsAmjrWUOXStLrGMBCrP6Xu6T2Ol7+7pt
 O+ZPZM5Xhmo0UR2sY4sWjDIC1AHVXaLZlbC7vfjadkZ30UZvwIXgDFJemS3nDW96
 /JJo/6sgdLGJGvNYGb4mitKO5+kIiz6kKeMvzcfBj+PWybfYhUbqc/AARtlf9Hzp
 +gvtFlCF
 =Q9hw
 -----END PGP SIGNATURE-----

Merge tag 'v2025.01-rc3' into next

Prepare v2025.01-rc3

.gitignore

@@ -75,6 +75,9 @@ fit-dtb.blob*
 /keep-syms-lto.*
 /*imx8mimage*
 /*imx8mcst*
+/drivers/video/u_boot_logo.S
+/test/overlay/test-fdt-overlay.dtbo.S
+/test/overlay/test-fdt-overlay-stacked.dtbo.S
 
 #
 # Generated include files
@@ -83,6 +86,8 @@ fit-dtb.blob*
 /include/config.h
 /include/config/
 /include/generated/
+/include/bmp_logo.h
+/include/bmp_logo_data.h
 
 # stgit generated dirs
 patches-*

.gitlab-ci.yml

@@ -3,6 +3,7 @@
 variables:
   DEFAULT_TAG: ""
   MIRROR_DOCKER: docker.io
+  SJG_LAB: ""
 
 default:
   tags:
@@ -16,6 +17,7 @@ image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240808-21Aug2024
 stages:
   - testsuites
   - test.py
+  - sjg-lab
   - world build
 
 .buildman_and_testpy_template: &buildman_and_testpy_dfn
@@ -521,3 +523,158 @@ coreboot test.py:
     TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id qemu"
   <<: *buildman_and_testpy_dfn
+
+.lab_template: &lab_dfn
+  stage: sjg-lab
+  rules:
+    - if: $SJG_LAB == "1"
+      when: always
+    - if: $SJG_LAB != "1"
+      when: manual
+      allow_failure: true
+  tags: [ 'lab' ]
+  script:
+    - if [[ -z "${SJG_LAB}" ]]; then
+        exit 0;
+      fi
+    # Environment:
+    #   SRC  - source tree
+    #   OUT  - output directory for builds
+    - export SRC="$(pwd)"
+    - export OUT="${SRC}/build/${BOARD}"
+    - export PATH=$PATH:~/bin
+    - export PATH=$PATH:/vid/software/devel/ubtest/u-boot-test-hooks/bin
+
+    # Load it on the device
+    - ret=0
+    - echo "role ${ROLE}"
+    - export strategy="-s uboot -e off"
+    - export USE_LABGRID_SJG=1
+    # export verbose="-v"
+    - ${SRC}/test/py/test.py --role ${ROLE} --build-dir "${OUT}"
+        --capture=tee-sys -k "not bootstd" || ret=$?
+    - U_BOOT_BOARD_IDENTITY="${ROLE}" u-boot-test-release || true
+    - if [[ $ret -ne 0 ]]; then
+        exit $ret;
+      fi
+  artifacts:
+    when: always
+    paths:
+      - "build/${BOARD}/test-log.html"
+      - "build/${BOARD}/multiplexed_log.css"
+    expire_in: 1 week
+
+rpi3:
+  variables:
+    ROLE: rpi3
+  <<: *lab_dfn
+
+opi_pc:
+  variables:
+    ROLE: opi_pc
+  <<: *lab_dfn
+
+pcduino3_nano:
+  variables:
+    ROLE: pcduino3_nano
+  <<: *lab_dfn
+
+samus:
+  variables:
+    ROLE: samus
+  <<: *lab_dfn
+
+link:
+  variables:
+    ROLE: link
+  <<: *lab_dfn
+
+jerry:
+  variables:
+    ROLE: jerry
+  <<: *lab_dfn
+
+minnowmax:
+  variables:
+    ROLE: minnowmax
+  <<: *lab_dfn
+
+opi_pc2:
+  variables:
+    ROLE: opi_pc2
+  <<: *lab_dfn
+
+bpi:
+  variables:
+    ROLE: bpi
+  <<: *lab_dfn
+
+rpi2:
+  variables:
+    ROLE: rpi2
+  <<: *lab_dfn
+
+bob:
+  variables:
+    ROLE: bob
+  <<: *lab_dfn
+
+ff3399:
+  variables:
+    ROLE: ff3399
+  <<: *lab_dfn
+
+coral:
+  variables:
+    ROLE: coral
+  <<: *lab_dfn
+
+rpi3z:
+  variables:
+    ROLE: rpi3z
+  <<: *lab_dfn
+
+bbb:
+  variables:
+    ROLE: bbb
+  <<: *lab_dfn
+
+kevin:
+  variables:
+    ROLE: kevin
+  <<: *lab_dfn
+
+pine64:
+  variables:
+    ROLE: pine64
+  <<: *lab_dfn
+
+c4:
+  variables:
+    ROLE: c4
+  <<: *lab_dfn
+
+rpi4:
+  variables:
+    ROLE: rpi4
+  <<: *lab_dfn
+
+rpi0:
+  variables:
+    ROLE: rpi0
+  <<: *lab_dfn
+
+snow:
+  variables:
+    ROLE: snow
+  <<: *lab_dfn
+
+pcduino3:
+  variables:
+    ROLE: pcduino3
+  <<: *lab_dfn
+
+nyan-big:
+  variables:
+    ROLE: nyan-big
+  <<: *lab_dfn

Kconfig

@@ -744,10 +744,15 @@ choice
 
 config NO_NET
 	bool "No networking support"
+	help
+	  Do not include networking support
 
 config NET
 	bool "Legacy U-Boot networking stack"
 	imply NETDEVICES
+	help
+	  Include networking support with U-Boot's internal implementation of
+	  the TCP/IP protocol stack.
 
 config NET_LWIP
 	bool "Use lwIP for networking stack"

MAINTAINERS

@@ -860,6 +860,7 @@ M:	Michal Simek <michal.simek@amd.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-zynqmp/
+F:	drivers/bootcount/bootcount_zynqmp.c
 F:	drivers/clk/clk_zynqmp.c
 F:	driver/firmware/firmware-zynqmp.c
 F:	drivers/fpga/zynqpl.c
@@ -1551,6 +1552,7 @@ SANDBOX
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
 F:	arch/sandbox/
+F:	configs/sandbox*
 F:	doc/arch/sandbox.rst
 F:	drivers/*/*sandbox*.c
 F:	include/dt-bindings/*/sandbox*.h
@@ -1697,6 +1699,7 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-tpm.git
 F:	cmd/tpm*
 F:	drivers/tpm/
 F:	include/tpm*
+F:	lib/tpm*
 
 TQ GROUP
 #M:	Martin Krause <martin.krause@tq-systems.de>

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2025
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
 NAME =
 
 # *DOCUMENTATION*
@@ -21,7 +21,7 @@ include include/host_arch.h
 ifeq ("", "$(CROSS_COMPILE)")
   MK_ARCH="${shell uname -m}"
 else
-  MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\2/p'}"
+  MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(ccache\)\?[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}"
 endif
 unexport HOST_ARCH
 ifeq ("x86_64", $(MK_ARCH))
@@ -1398,7 +1398,8 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
                 --toolpath $(objtree)/tools \
 		$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
 		build -u -d u-boot.dtb -O . -m \
-		--allow-missing $(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
+		--allow-missing --fake-ext-blobs \
+		$(if $(BINMAN_ALLOW_MISSING),--ignore-missing) \
 		-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
 		$(foreach f,$(of_list_dirs),-I $(f)) -a of-list=$(of_list) \
 		$(foreach f,$(BINMAN_INDIRS),-I $(f)) \

arch/Kconfig

@@ -8,6 +8,11 @@ config CREATE_ARCH_SYMLINK
 config HAVE_ARCH_IOREMAP
 	bool
 
+config HAVE_SETJMP
+	bool
+	help
+	 The architecture supports setjmp() and longjmp().
+
 config SUPPORT_BIG_ENDIAN
 	bool
 
@@ -73,6 +78,7 @@ config ARC
 
 config ARM
 	bool "ARM architecture"
+	select HAVE_SETJMP
 	select ARCH_SUPPORTS_LTO
 	select CREATE_ARCH_SYMLINK
 	select HAVE_PRIVATE_LIBGCC if !ARM64
@@ -129,6 +135,7 @@ config PPC
 config RISCV
 	bool "RISC-V architecture"
 	select CREATE_ARCH_SYMLINK
+	select HAVE_SETJMP
 	select SUPPORT_ACPI
 	select SUPPORT_LITTLE_ENDIAN
 	select SUPPORT_OF_CONTROL
@@ -154,6 +161,7 @@ config RISCV
 
 config SANDBOX
 	bool "Sandbox"
+	select HAVE_SETJMP
 	select ARCH_SUPPORTS_LTO
 	select BOARD_LATE_INIT
 	select BZIP2
@@ -249,6 +257,7 @@ config SH
 
 config X86
 	bool "x86 architecture"
+	select HAVE_SETJMP
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select SUPPORT_LITTLE_ENDIAN

arch/arm/dts/imx8mn-u-boot.dtsi

@@ -68,6 +68,11 @@
 	bootph-all;
 };
 
+&osc_32k {
+	bootph-pre-ram;
+	bootph-all;
+};
+
 #ifdef CONFIG_FSL_CAAM
 &sec_jr0 {
 	bootph-pre-ram;

arch/arm/dts/k3-am625-phycore-som-binman.dtsi

@@ -301,6 +301,54 @@
 					description = "U-Boot for phyCORE-AM62x";
 				};
 
+				som-no-rtc {
+					description = "k3-am6xx-phycore-disable-rtc";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F000000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtbo";
+					};
+				};
+
+				som-no-spi {
+					description = "k3-am6xx-phycore-disable-spi-nor";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F001000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtbo";
+					};
+				};
+
+				som-no-eth {
+					description = "k3-am6xx-phycore-disable-eth-phy";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F002000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtbo";
+					};
+				};
+
+				som-qspi {
+					description = "k3-am6xx-phycore-qspi-nor";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F003000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtbo";
+					};
+				};
+
 				fdt-0 {
 					description = "k3-am625-phyboard-lyra-rdk";
 					type = "flat_dt";
@@ -325,7 +373,11 @@
 				conf-0 {
 					description = "k3-am625-phyboard-lyra-rdk";
 					firmware = "uboot";
-					loadables = "uboot";
+					loadables = "uboot",
+						    "som-no-rtc",
+						    "som-no-spi",
+						    "som-no-eth",
+						    "som-qspi";
 					fdt = "fdt-0";
 				};
 			};

arch/arm/dts/k3-am642-phycore-som-binman.dtsi

@@ -344,6 +344,54 @@
 					description = "U-Boot for AM64 board";
 				};
 
+				som-no-rtc {
+					description = "k3-am6xx-phycore-disable-rtc";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F000000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-rtc.dtbo";
+					};
+				};
+
+				som-no-spi {
+					description = "k3-am6xx-phycore-disable-spi-nor";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F001000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-spi-nor.dtbo";
+					};
+				};
+
+				som-no-eth {
+					description = "k3-am6xx-phycore-disable-eth-phy";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F002000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-disable-eth-phy.dtbo";
+					};
+				};
+
+				som-qspi {
+					description = "k3-am6xx-phycore-qspi-nor";
+					type = "flat_dt";
+					compression = "none";
+					load = <0x8F003000>;
+					arch = "arm";
+
+					blob-ext {
+						filename = "dts/upstream/src/arm64/ti/k3-am6xx-phycore-qspi-nor.dtbo";
+					};
+				};
+
 				fdt-0 {
 					description = "k3-am642-phyboard-electra-rdk";
 					type = "flat_dt";
@@ -368,7 +416,11 @@
 				conf-0 {
 					description = "k3-am642-phyboard-electra-rdk";
 					firmware = "uboot";
-					loadables = "uboot";
+					loadables = "uboot",
+						    "som-no-rtc",
+						    "som-no-spi",
+						    "som-no-eth",
+						    "som-qspi";
 					fdt = "fdt-0";
 				};
 			};

arch/arm/dts/stm32mp13xx-dhcor-som.dtsi

@@ -1,308 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2024 Marek Vasut <marex@denx.de>
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/mfd/st,stpmic1.h>
-#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
-#include "stm32mp13-pinctrl.dtsi"
-
-/ {
-	model = "DH electronics STM32MP13xx DHCOR SoM";
-	compatible = "dh,stm32mp131a-dhcor-som",
-		     "st,stm32mp131";
-
-	aliases {
-		mmc0 = &sdmmc2;
-		mmc1 = &sdmmc1;
-		serial0 = &uart4;
-		serial1 = &uart7;
-		rtc0 = &rv3032;
-		spi0 = &qspi;
-	};
-
-	memory@c0000000 {
-		device_type = "memory";
-		reg = <0xc0000000 0x20000000>;
-	};
-
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		optee@dd000000 {
-			reg = <0xdd000000 0x3000000>;
-			no-map;
-		};
-	};
-
-	sdio_pwrseq: sdio-pwrseq {
-		compatible = "mmc-pwrseq-simple";
-		reset-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>;
-	};
-
-	vin: vin {
-		compatible = "regulator-fixed";
-		regulator-name = "vin";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
-	};
-};
-
-&i2c3 {
-	i2c-scl-rising-time-ns = <96>;
-	i2c-scl-falling-time-ns = <3>;
-	clock-frequency = <400000>;
-	status = "okay";
-	/* spare dmas for other usage */
-	/delete-property/dmas;
-	/delete-property/dma-names;
-
-	pmic: stpmic@33 {
-		compatible = "st,stpmic1";
-		reg = <0x33>;
-		interrupts-extended = <&gpioi 3 IRQ_TYPE_EDGE_FALLING>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-		status = "okay";
-
-		regulators {
-			compatible = "st,stpmic1-regulators";
-
-			ldo1-supply = <&vin>;
-			ldo2-supply = <&vin>;
-			ldo3-supply = <&vin>;
-			ldo4-supply = <&vin>;
-			ldo5-supply = <&vin>;
-			ldo6-supply = <&vin>;
-			pwr_sw1-supply = <&bst_out>;
-			pwr_sw2-supply = <&bst_out>;
-
-			vddcpu: buck1 { /* VDD_CPU_1V2 */
-				regulator-name = "vddcpu";
-				regulator-min-microvolt = <1250000>;
-				regulator-max-microvolt = <1250000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			vdd_ddr: buck2 { /* VDD_DDR_1V35 */
-				regulator-name = "vdd_ddr";
-				regulator-min-microvolt = <1350000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			vdd: buck3 { /* VDD_3V3_1V8 */
-				regulator-name = "vdd";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			vddcore: buck4 { /* VDD_CORE_1V2 */
-				regulator-name = "vddcore";
-				regulator-min-microvolt = <1250000>;
-				regulator-max-microvolt = <1250000>;
-				regulator-always-on;
-				regulator-initial-mode = <0>;
-				regulator-over-current-protection;
-			};
-
-			vdd_adc: ldo1 { /* VDD_ADC_1V8 */
-				regulator-name = "vdd_adc";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				interrupts = <IT_CURLIM_LDO1 0>;
-			};
-
-			vdd_ldo2: ldo2 { /* LDO2_OUT_1V8 */
-				regulator-name = "vdd_ldo2";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				interrupts = <IT_CURLIM_LDO2 0>;
-			};
-
-			vdd_ldo3: ldo3 { /* LDO3_OUT */
-				regulator-name = "vdd_ldo3";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				interrupts = <IT_CURLIM_LDO3 0>;
-			};
-
-			vdd_usb: ldo4 { /* VDD_USB_3V3 */
-				regulator-name = "vdd_usb";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				interrupts = <IT_CURLIM_LDO4 0>;
-			};
-
-			vdd_sd: ldo5 { /* VDD_SD_3V3_1V8 */
-				regulator-name = "vdd_sd";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				interrupts = <IT_CURLIM_LDO5 0>;
-			};
-
-			vdd_sd2: ldo6 { /* VDD_SD2_3V3_1V8 */
-				regulator-name = "vdd_sd2";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				interrupts = <IT_CURLIM_LDO6 0>;
-			};
-
-			vref_ddr: vref_ddr { /* VREF_DDR_0V675 */
-				regulator-name = "vref_ddr";
-				regulator-always-on;
-			};
-
-			bst_out: boost { /* BST_OUT_5V2 */
-				regulator-name = "bst_out";
-			};
-
-			vbus_otg: pwr_sw1 {
-				regulator-name = "vbus_otg";
-				interrupts = <IT_OCP_OTG 0>;
-			};
-
-			vbus_sw: pwr_sw2 {
-				regulator-name = "vbus_sw";
-				interrupts = <IT_OCP_SWOUT 0>;
-				regulator-active-discharge = <1>;
-			};
-		};
-
-		onkey {
-			compatible = "st,stpmic1-onkey";
-			interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>;
-			interrupt-names = "onkey-falling", "onkey-rising";
-			status = "okay";
-		};
-
-		watchdog {
-			compatible = "st,stpmic1-wdt";
-			status = "disabled";
-		};
-	};
-
-	eeprom0: eeprom@50 {
-		compatible = "atmel,24c256";	/* ST M24256 */
-		reg = <0x50>;
-		pagesize = <64>;
-	};
-
-	rv3032: rtc@51 {
-		compatible = "microcrystal,rv3032";
-		reg = <0x51>;
-		interrupts-extended = <&gpioi 0 IRQ_TYPE_EDGE_FALLING>;
-	};
-};
-
-&iwdg2 {
-	timeout-sec = <32>;
-	status = "okay";
-};
-
-&qspi {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&qspi_clk_pins_a
-		     &qspi_bk1_pins_a
-		     &qspi_cs1_pins_a>;
-	pinctrl-1 = <&qspi_clk_sleep_pins_a
-		     &qspi_bk1_sleep_pins_a
-		     &qspi_cs1_sleep_pins_a>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "okay";
-
-	flash0: flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-rx-bus-width = <4>;
-		spi-max-frequency = <108000000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-	};
-};
-
-/* Console UART */
-&uart4 {
-	pinctrl-names = "default", "sleep", "idle";
-	pinctrl-0 = <&uart4_pins_b>;
-	pinctrl-1 = <&uart4_sleep_pins_b>;
-	pinctrl-2 = <&uart4_idle_pins_b>;
-	/delete-property/dmas;
-	/delete-property/dma-names;
-	status = "okay";
-};
-
-/* Bluetooth */
-&uart7 {
-	pinctrl-names = "default", "sleep", "idle";
-	pinctrl-0 = <&uart7_pins_a>;
-	pinctrl-1 = <&uart7_sleep_pins_a>;
-	pinctrl-2 = <&uart7_idle_pins_a>;
-	uart-has-rtscts;
-	status = "okay";
-
-	bluetooth {
-		compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
-		max-speed = <3000000>;
-		device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>;
-		shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-/* SDIO WiFi */
-&sdmmc1 {
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
-	pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
-	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
-	bus-width = <4>;
-	cap-power-off-card;
-	keep-power-in-suspend;
-	non-removable;
-	st,neg-edge;
-	vmmc-supply = <&vdd>;
-	mmc-pwrseq = <&sdio_pwrseq>;
-	status = "okay";
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	brcmf: bcrmf@1 {	/* muRata 1YN */
-		reg = <1>;
-		compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac";
-		interrupt-parent = <&gpioe>;
-		interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-names = "host-wake";
-	};
-};
-
-/* eMMC */
-&sdmmc2 {
-	pinctrl-names = "default", "opendrain", "sleep";
-	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>;
-	pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>;
-	pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
-	bus-width = <8>;
-	mmc-ddr-3_3v;
-	no-sd;
-	no-sdio;
-	non-removable;
-	st,neg-edge;
-	vmmc-supply = <&vdd>;
-	vqmmc-supply = <&vdd>;
-	status = "okay";
-};

arch/arm/dts/stm32mp153c-dhcor-drc-compact.dts

@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) 2022 Marek Vasut <marex@denx.de>
- *
- * DHCOR STM32MP1 variant:
- * DHCR-STM32MP153C-C065-R051-V33-SPI-I-01LG
- * DHCOR PCB number: 586-100 or newer
- * DRC Compact PCB number: 627-100 or newer
- */
-
-/dts-v1/;
-
-#include "stm32mp153.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15xx-dhcor-som.dtsi"
-#include "stm32mp15xx-dhcor-drc-compact.dtsi"
-
-/ {
-	model = "DH electronics STM32MP153C DHCOR DRC Compact";
-	compatible = "dh,stm32mp153c-dhcor-drc-compact",
-		     "dh,stm32mp153c-dhcor-som",
-		     "st,stm32mp153";
-};
-
-&m_can1 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&m_can1_pins_c>;
-	pinctrl-1 = <&m_can1_sleep_pins_c>;
-	status = "okay";
-};

arch/arm/dts/stm32mp157a-dhcor-avenger96.dts

@@ -1,38 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
-/*
- * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
- * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- * Copyright (C) 2020 Marek Vasut <marex@denx.de>
- *
- * DHCOR STM32MP1 variant:
- * DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG
- * DHCOR PCB number: 586-100 or newer
- * Avenger96 PCB number: 588-200 or newer
- */
-
-/dts-v1/;
-
-#include "stm32mp157.dtsi"
-#include "stm32mp15xc.dtsi"
-#include "stm32mp15xx-dhcor-som.dtsi"
-#include "stm32mp15xx-dhcor-avenger96.dtsi"
-
-/ {
-	model = "Arrow Electronics STM32MP157A Avenger96 board";
-	compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som",
-		     "st,stm32mp157";
-};
-
-&m_can1 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&m_can1_pins_b>;
-	pinctrl-1 = <&m_can1_sleep_pins_b>;
-	status = "disabled";
-};
-
-&m_can2 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&m_can2_pins_a>;
-	pinctrl-1 = <&m_can2_sleep_pins_a>;
-	status = "disabled";
-};

arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi

@@ -12,6 +12,7 @@
 
 / {
 	aliases {
+		eeprom0 = &eeprom0;
 		i2c1 = &i2c2;
 		i2c3 = &i2c4;
 		i2c4 = &i2c5;
@@ -19,15 +20,14 @@
 		mmc1 = &sdmmc2;
 		spi0 = &qspi;
 		usb0 = &usbotg_hs;
-		eeprom0 = &eeprom0;
 	};
 
 	config {
-		u-boot,boot-led = "heartbeat";
-		u-boot,error-led = "error";
-		dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
 		dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
 		dh,mac-coding-gpios = <&gpioc 3 0>;
+		dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
+		u-boot,boot-led = "heartbeat";
+		u-boot,error-led = "error";
 	};
 };
 
@@ -36,17 +36,6 @@
 	/delete-property/ st,eth-ref-clk-sel;
 };
 
-&ethernet0_rmii_pins_a {
-	pins1 {
-		pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
-			 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
-			 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
-			 <STM32_PINMUX('A', 1, AF11)>,  /* ETH1_RMII_REF_CLK */
-			 <STM32_PINMUX('A', 2, AF11)>,  /* ETH1_MDIO */
-			 <STM32_PINMUX('C', 1, AF11)>;  /* ETH1_MDC */
-	};
-};
-
 &i2c4 {
 	bootph-all;
 	bootph-pre-ram;
@@ -62,36 +51,6 @@
 	};
 };
 
-&phy0 {
-	/delete-property/ reset-gpios;
-};
-
-&pinctrl {
-	mco2_pins_a: mco2-0 {
-		pins {
-			pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
-			bias-disable;
-			drive-push-pull;
-			slew-rate = <2>;
-		};
-	};
-
-	mco2_sleep_pins_a: mco2-sleep-0 {
-		pins {
-			pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
-		};
-	};
-};
-
-&pmic {
-	bootph-all;
-	bootph-pre-ram;
-
-	regulators {
-		bootph-pre-ram;
-	};
-};
-
 &flash0 {
 	bootph-pre-ram;
 
@@ -123,6 +82,19 @@
 	};
 };
 
+&phy0 {
+	/delete-property/ reset-gpios;
+};
+
+&pmic {
+	bootph-all;
+	bootph-pre-ram;
+
+	regulators {
+		bootph-pre-ram;
+	};
+};
+
 &qspi {
 	bootph-pre-ram;
 };
@@ -269,6 +241,14 @@
 	};
 };
 
+&reg11 {
+	bootph-pre-ram;
+};
+
+&reg18 {
+	bootph-pre-ram;
+};
+
 &sdmmc1 {
 	bootph-pre-ram;
 	st,use-ckin;
@@ -331,14 +311,6 @@
 	};
 };
 
-&reg11 {
-	bootph-pre-ram;
-};
-
-&reg18 {
-	bootph-pre-ram;
-};
-
 &usb33 {
 	bootph-pre-ram;
 };

arch/arm/dts/zynqmp-sc-revB.dts

@@ -3,7 +3,7 @@
  * dts file for Xilinx ZynqMP Generic System Controller
  *
  * (C) Copyright 2021 - 2022, Xilinx, Inc.
- * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2022 - 2024, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -80,7 +80,7 @@
 	pwm-fan {
 		compatible = "pwm-fan";
 		status = "okay";
-		pwms = <&ttc0 2 40000 1>;
+		pwms = <&ttc0 2 40000 0>;
 	};
 };
 

arch/arm/dts/zynqmp-sm-k26-revA.dts

@@ -387,6 +387,7 @@
 
 &rtc {
 	status = "okay";
+	calibration = <0x7fff>;
 };
 
 &lpd_dma_chan1 {

arch/arm/lib/bootm.c

@@ -73,11 +73,10 @@ static void announce_and_cleanup(int fake)
 	 * Call remove function of all devices with a removal flag set.
 	 * This may be useful for last-stage operations, like cancelling
 	 * of DMA operation or releasing device internal buffers.
+	 * dm_remove_devices_active() ensures that vital devices are removed in
+	 * a second round.
 	 */
-	dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL);
-
-	/* Remove all active vital devices next */
-	dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+	dm_remove_devices_active();
 
 	cleanup_before_linux();
 }

arch/arm/mach-aspeed/ast2600/spl.c

@@ -45,10 +45,10 @@ u32 spl_boot_device(void)
 	}
 
 	/* boot from UART has higher priority */
-	if (scu->hwstrap2 & SCU_HWSTRAP2_BOOT_UART)
+	if (readl(&scu->hwstrap2) & SCU_HWSTRAP2_BOOT_UART)
 		return BOOT_DEVICE_UART;
 
-	if (scu->hwstrap1 & SCU_HWSTRAP1_BOOT_EMMC)
+	if (readl(&scu->hwstrap1) & SCU_HWSTRAP1_BOOT_EMMC)
 		return BOOT_DEVICE_MMC1;
 
 out:

arch/arm/mach-imx/fdt.c

@@ -115,7 +115,7 @@ int fixup_thermal_trips(void *blob, const char *name)
 
 		temp = 0;
 		if (!strcmp(type, "critical"))
-			temp = 1000 * (maxc - 5);
+			temp = 1000 * maxc;
 		else if (!strcmp(type, "passive"))
 			temp = 1000 * (maxc - 10);
 		if (temp) {

arch/arm/mach-snapdragon/Kconfig

@@ -11,6 +11,9 @@ config SYS_VENDOR
 	  Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
 	  will be used as the custom board directory.
 
+config SYS_MALLOC_LEN
+	default 0x10000000
+
 config SYS_MALLOC_F_LEN
 	default 0x2000
 
@@ -20,6 +23,9 @@ config SPL_SYS_MALLOC_F
 config SPL_SYS_MALLOC_F_LEN
 	default 0x2000
 
+config SYS_MALLOC_LEN
+	default 0x800000
+
 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
 	default 0x80000000
 

arch/arm/mach-snapdragon/Makefile

@@ -3,4 +3,5 @@
 # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 
 obj-y += board.o
+obj-$(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) += capsule_update.o
 obj-$(CONFIG_OF_LIVE) += of_fixup.o

arch/arm/mach-snapdragon/board.c

@@ -6,7 +6,9 @@
  * Author: Caleb Connolly <caleb.connolly@linaro.org>
  */
 
-#include "time.h"
+#define LOG_CATEGORY LOGC_BOARD
+#define pr_fmt(fmt) "QCOM: " fmt
+
 #include <asm/armv8/mmu.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -29,6 +31,7 @@
 #include <fdt_support.h>
 #include <usb.h>
 #include <sort.h>
+#include <time.h>
 
 #include "qcom-priv.h"
 
@@ -448,6 +451,9 @@ int board_late_init(void)
 	configure_env();
 	qcom_late_init();
 
+	/* Configure the dfu_string for capsule updates */
+	qcom_configure_capsule_updates();
+
 	return 0;
 }
 

arch/arm/mach-snapdragon/capsule_update.c

@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Capsule update support for Qualcomm boards.
+ *
+ * Copyright (c) 2024 Linaro Ltd.
+ * Author: Caleb Connolly <caleb.connolly@linaro.org>
+ */
+
+#define pr_fmt(fmt) "QCOM-FMP: " fmt
+
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <efi.h>
+#include <efi_loader.h>
+#include <malloc.h>
+#include <scsi.h>
+#include <part.h>
+#include <linux/err.h>
+
+#include "qcom-priv.h"
+
+/*
+ * NOTE: for now this implementation only supports the rb3gen2. Supporting other
+ * boards that boot in different ways (e.g. chainloaded from ABL) will require
+ * additional complexity to properly create the dfu string and fw_images array.
+ */
+
+/*
+ * To handle different variants like chainloaded U-Boot here we'll need to
+ * build the fw_images array dynamically at runtime. It looks like
+ * mach-rockchip is a good example for how to do this.
+ * Detecting which image types a board uses is TBD, hence for now we only
+ * support the one new board that runs U-Boot as its primary bootloader.
+ */
+struct efi_fw_image fw_images[] = {
+	{
+		/* U-Boot flashed to the uefi_X partition (e.g. rb3gen2) */
+		.fw_name = u"UBOOT_UEFI_PARTITION",
+		.image_index = 1,
+	},
+};
+
+struct efi_capsule_update_info update_info = {
+	/* Filled in by configure_dfu_string() */
+	.dfu_string = NULL,
+	.num_images = ARRAY_SIZE(fw_images),
+	.images = fw_images,
+};
+
+/* LSB first */
+struct part_slot_status {
+	u16: 2;
+	u16 active : 1;
+	u16: 3;
+	u16 successful : 1;
+	u16 unbootable : 1;
+	u16 tries_remaining : 4;
+};
+
+static int find_boot_partition(const char *partname, struct blk_desc *blk_dev, char *name)
+{
+	int ret;
+	int partnum;
+	struct disk_partition info;
+	struct part_slot_status *slot_status;
+
+	for (partnum = 1;; partnum++) {
+		ret = part_get_info(blk_dev, partnum, &info);
+		if (ret)
+			return ret;
+
+		slot_status = (struct part_slot_status *)&info.type_flags;
+		log_io("%16s: Active: %1d, Successful: %1d, Unbootable: %1d, Tries left: %1d\n",
+		       info.name, slot_status->active,
+		       slot_status->successful, slot_status->unbootable,
+		       slot_status->tries_remaining);
+		/*
+		 * FIXME: eventually we'll want to find the active/inactive variant of the partition
+		 * but on the rb3gen2 these values might all be 0
+		 */
+		if (!strncmp(info.name, partname, strlen(partname))) {
+			log_debug("Found active %s partition: '%s'!\n", partname, info.name);
+			strlcpy(name, info.name, sizeof(info.name));
+			return partnum;
+		}
+	}
+
+	return -1;
+}
+
+/**
+ * qcom_configure_capsule_updates() - Configure the DFU string for capsule updates
+ *
+ * U-Boot is flashed to the boot partition on Qualcomm boards. In most cases there
+ * are two boot partitions, boot_a and boot_b. As we don't currently support doing
+ * full A/B updates, we only support updating the currently active boot partition.
+ *
+ * So we need to find the current slot suffix and the associated boot partition.
+ * We do this by looking for the boot partition that has the 'active' flag set
+ * in the GPT partition vendor attribute bits.
+ */
+void qcom_configure_capsule_updates(void)
+{
+	struct blk_desc *desc;
+	int ret = 0, partnum = -1, devnum;
+	static char dfu_string[32] = { 0 };
+	char name[32]; /* GPT partition name */
+	char *partname = "uefi_a";
+	struct udevice *dev = NULL;
+
+	if (IS_ENABLED(CONFIG_SCSI)) {
+		/* Scan for SCSI devices */
+		ret = scsi_scan(false);
+		if (ret) {
+			debug("Failed to scan SCSI devices: %d\n", ret);
+			return;
+		}
+	}
+
+	uclass_foreach_dev_probe(UCLASS_BLK, dev) {
+		if (device_get_uclass_id(dev) != UCLASS_BLK)
+			continue;
+
+		desc = dev_get_uclass_plat(dev);
+		if (!desc || desc->part_type == PART_TYPE_UNKNOWN)
+			continue;
+		devnum = desc->devnum;
+		partnum = find_boot_partition(partname, desc,
+					      name);
+		if (partnum >= 0)
+			break;
+	}
+
+	if (partnum < 0) {
+		log_err("Failed to find boot partition\n");
+		return;
+	}
+
+	switch (desc->uclass_id) {
+	case UCLASS_SCSI:
+		snprintf(dfu_string, 32, "scsi %d=u-boot.bin part %d", devnum, partnum);
+		break;
+	case UCLASS_MMC:
+		snprintf(dfu_string, 32, "mmc 0=u-boot.bin part %d %d", devnum, partnum);
+		break;
+	default:
+		debug("Unsupported storage uclass: %d\n", desc->uclass_id);
+		return;
+	}
+	log_debug("boot partition is %s, DFU string: '%s'\n", name, dfu_string);
+
+	update_info.dfu_string = dfu_string;
+}

arch/arm/mach-snapdragon/qcom-priv.h

@@ -3,6 +3,12 @@
 #ifndef __QCOM_PRIV_H__
 #define __QCOM_PRIV_H__
 
+#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
+void qcom_configure_capsule_updates(void);
+#else
+void qcom_configure_capsule_updates(void) {}
+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
+
 #if CONFIG_IS_ENABLED(OF_LIVE)
 /**
  * qcom_of_fixup_nodes() - Fixup Qualcomm DT nodes

arch/arm/mach-zynqmp/include/mach/hardware.h

@@ -188,6 +188,8 @@ struct pmu_regs {
 	u32 gen_storage4; /* 0x40 */
 	u32 reserved1[1];
 	u32 gen_storage6; /* 0x48 */
+	u32 reserved2[3];
+	u32 pers_gen_storage2; /* 0x58 */
 };
 
 #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)

arch/arm/mach-zynqmp/mp.c

@@ -352,7 +352,7 @@ int cpu_release(u32 nr, int argc, char *const argv[])
 		 */
 		flush_dcache_all();
 
-		if (!strncmp(argv[1], "lockstep", 8)) {
+		if (!strcmp(argv[1], "lockstep") || !strcmp(argv[1], "0")) {
 			if (nr != ZYNQMP_CORE_RPU0) {
 				printf("Lockstep mode should run on ZYNQMP_CORE_RPU0\n");
 				return 1;
@@ -369,7 +369,7 @@ int cpu_release(u32 nr, int argc, char *const argv[])
 			dcache_enable();
 			set_r5_halt_mode(nr, RELEASE, LOCK);
 			mark_r5_used(nr, LOCK);
-		} else if (!strncmp(argv[1], "split", 5)) {
+		} else if (!strcmp(argv[1], "split") || !strcmp(argv[1], "1")) {
 			printf("R5 split mode\n");
 			set_r5_reset(nr, SPLIT);
 			set_r5_tcm_mode(SPLIT);

arch/riscv/lib/bootm.c

@@ -57,7 +57,7 @@ static void announce_and_cleanup(int fake)
 	 * This may be useful for last-stage operations, like cancelling
 	 * of DMA operation or releasing device internal buffers.
 	 */
-	dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+	dm_remove_devices_active();
 
 	cleanup_before_linux();
 }

arch/x86/lib/bootm.c

@@ -49,7 +49,7 @@ void bootm_announce_and_cleanup(void)
 	 * This may be useful for last-stage operations, like cancelling
 	 * of DMA operation or releasing device internal buffers.
 	 */
-	dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+	dm_remove_devices_active();
 }
 
 #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)

board/armltd/total_compute/MAINTAINERS

@@ -1,5 +1,5 @@
 TOTAL_COMPUTE BOARD
-M:	Usama Arif <usama.arif@arm.com>
+M:	Ben Horgan <ben.horgan@arm.com>
 S:	Maintained
 F:	board/armltd/total_compute/
 F:	include/configs/total_compute.h

board/emulation/qemu-arm/Kconfig

@@ -5,6 +5,7 @@ config TEXT_BASE
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
+	select HAS_CUSTOM_SYS_INIT_SP_ADDR
 	select QFW if ACPI
 	select QFW_MMIO if CMD_QFW
 	imply VIRTIO_MMIO

board/phytec/common/k3/board.c

@@ -6,7 +6,9 @@
 
 #include <env_internal.h>
 #include <fdt_support.h>
+#include <dm/ofnode.h>
 #include <spl.h>
+#include <malloc.h>
 #include <asm/arch/hardware.h>
 
 #include "../am6_som_detection.h"
@@ -97,8 +99,79 @@ int board_late_init(void)
 #endif
 
 #if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
+static int fdt_apply_overlay_from_fit(const char *overlay_path, void *fdt)
+{
+	u64 loadaddr;
+	ofnode node;
+	int ret;
+
+	node = ofnode_path(overlay_path);
+	if (!ofnode_valid(node))
+		return -FDT_ERR_NOTFOUND;
+
+	ret = ofnode_read_u64(node, "load", &loadaddr);
+	if (ret)
+		return ret;
+
+	return fdt_overlay_apply_verbose(fdt, (void *)loadaddr);
+}
+
+static void fdt_apply_som_overlays(void *blob)
+{
+	void *fdt_copy;
+	u32 fdt_size;
+	struct phytec_eeprom_data data;
+	int err;
+
+	fdt_size = fdt_totalsize(blob);
+	fdt_copy = malloc(fdt_size);
+	if (!fdt_copy)
+		goto fixup_error;
+
+	memcpy(fdt_copy, blob, fdt_size);
+
+	err = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR);
+	if (err)
+		goto fixup_error;
+
+	if (phytec_get_am6_rtc(&data) == 0) {
+		err = fdt_apply_overlay_from_fit("/fit-images/som-no-rtc", fdt_copy);
+		if (err)
+			goto fixup_error;
+	}
+
+	if (phytec_get_am6_spi(&data) == PHYTEC_EEPROM_VALUE_X) {
+		err = fdt_apply_overlay_from_fit("/fit-images/som-no-spi", fdt_copy);
+		if (err)
+			goto fixup_error;
+	}
+
+	if (phytec_get_am6_eth(&data) == 0) {
+		err = fdt_apply_overlay_from_fit("/fit-images/som-no-eth", fdt_copy);
+		if (err)
+			goto fixup_error;
+	}
+
+	if (phytec_am6_is_qspi(&data)) {
+		err = fdt_apply_overlay_from_fit("/fit-images/som-qspi-nor", fdt_copy);
+		if (err)
+			goto fixup_error;
+	}
+
+	memcpy(blob, fdt_copy, fdt_size);
+
+cleanup:
+	free(fdt_copy);
+	return;
+
+fixup_error:
+	pr_err("Failed to apply SoM overlays\n");
+	goto cleanup;
+}
+
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
+	fdt_apply_som_overlays(blob);
 	fdt_copy_fixed_partitions(blob);
 
 	return 0;

board/xilinx/Kconfig

@@ -40,6 +40,15 @@ config XILINX_PS_INIT_FILE
 
 endif
 
+config XILINX_MINI
+	bool "Mini configuration"
+	depends on ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
+	help
+	  This option disables features which are not needed for Mini U-Boot
+	  configurations. Mini U-Boot is running in EL3 mostly on size contrained
+	  systems. It's purpose is to program non volatile memories or running
+	  initial memory tests.
+
 config XILINX_OF_BOARD_DTB_ADDR
 	hex "Default DTB pickup address"
 	default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2

board/xilinx/common/board.c

@@ -19,6 +19,7 @@
 #include <i2c.h>
 #include <linux/sizes.h>
 #include <malloc.h>
+#include <memtop.h>
 #include <mtd_node.h>
 #include "board.h"
 #include <dm.h>
@@ -676,3 +677,31 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	return 0;
 }
 #endif
+
+#ifndef CONFIG_XILINX_MINI
+
+#ifndef MMU_SECTION_SIZE
+#define MMU_SECTION_SIZE        (1 * 1024 * 1024)
+#endif
+
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
+{
+	phys_size_t size;
+	phys_addr_t reg;
+
+	if (!total_size)
+		return gd->ram_top;
+
+	if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8))
+		panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob);
+
+	size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
+	reg = get_mem_top(gd->ram_base, gd->ram_size, size,
+			  (void *)gd->fdt_blob);
+	if (!reg)
+		reg = gd->ram_top - size;
+
+	return reg + size;
+}
+
+#endif

board/xilinx/versal/board.c

@@ -12,12 +12,15 @@
 #include <env_internal.h>
 #include <log.h>
 #include <malloc.h>
+#include <memalign.h>
+#include <mmc.h>
 #include <time.h>
 #include <asm/cache.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
+#include <linux/sizes.h>
 #include <dm/device.h>
 #include <dm/uclass.h>
 #include <versalpl.h>
@@ -301,9 +304,11 @@ int dram_init(void)
 	return 0;
 }
 
+#if !CONFIG_IS_ENABLED(SYSRESET)
 void reset_cpu(void)
 {
 }
+#endif
 
 #if defined(CONFIG_ENV_IS_NOWHERE)
 enum env_location env_get_location(enum env_operation op, int prio)
@@ -336,3 +341,41 @@ enum env_location env_get_location(enum env_operation op, int prio)
 	}
 }
 #endif
+
+#if defined(CONFIG_SET_DFU_ALT_INFO)
+
+#define DFU_ALT_BUF_LEN		SZ_1K
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+	int bootseq = 0, len = 0;
+	u32 bootmode = versal_get_bootmode();
+
+	ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+
+	if (env_get("dfu_alt_info"))
+		return;
+
+	memset(buf, 0, sizeof(buf));
+
+	switch (bootmode) {
+	case EMMC_MODE:
+	case SD_MODE:
+	case SD1_LSHFT_MODE:
+	case SD_MODE1:
+		bootseq = mmc_get_env_dev();
+
+		len += snprintf(buf + len, DFU_ALT_BUF_LEN, "mmc %d=boot",
+			       bootseq);
+
+		len += snprintf(buf + len, DFU_ALT_BUF_LEN, ".bin fat %d 1",
+			       bootseq);
+		break;
+	default:
+		return;
+	}
+
+	env_set("dfu_alt_info", buf);
+	puts("DFU alt info setting: done\n");
+}
+#endif

board/xilinx/zynqmp/zynqmp_kria.env

@@ -77,6 +77,7 @@ tpm_kv260=if test ${card1_rev} = A -o ${card1_rev} = B -o ${card1_rev} = Y -o ${
 tpm_kd240=if test ${card1_rev} = A; then run tpm_reset; fi
 
 board_setup=\
+rtc dev 0; \
 zynqmp mmio_write 0xFFCA0010 0xfff 0; \
 if test ${card1_name} = SCK-KV-G; then run kv260_setup; run tpm_kv260; fi;\
 if test ${card1_name} = SCK-KR-G; then run kr260_setup; run tpm_reset; fi;\

boot/bootmeth_extlinux.c

@@ -8,6 +8,7 @@
 
 #define LOG_CATEGORY UCLASS_BOOTSTD
 
+#include <asm/cache.h>
 #include <bootdev.h>
 #include <bootflow.h>
 #include <bootmeth.h>
@@ -159,7 +160,7 @@ static int extlinux_read_bootflow(struct udevice *dev, struct bootflow *bflow)
 		return log_msg_ret("try", ret);
 	size = bflow->size;
 
-	ret = bootmeth_alloc_file(bflow, 0x10000, 1);
+	ret = bootmeth_alloc_file(bflow, 0x10000, ARCH_DMA_MINALIGN);
 	if (ret)
 		return log_msg_ret("read", ret);
 

boot/image-board.c

@@ -624,9 +624,10 @@ int boot_get_fpga(struct bootm_headers *images)
 	void *buf;
 	int conf_noffset;
 	int fit_img_result;
-	const char *uname, *name;
+	const char *uname, *name, *compatible;
 	int err;
 	int devnum = 0; /* TODO support multi fpga platforms */
+	int flags = 0;
 
 	if (!IS_ENABLED(CONFIG_FPGA))
 		return -ENOSYS;
@@ -674,20 +675,29 @@ int boot_get_fpga(struct bootm_headers *images)
 			return fit_img_result;
 		}
 
+		conf_noffset = fit_image_get_node(buf, uname);
+		compatible = fdt_getprop(buf, conf_noffset, "compatible", NULL);
+		if (!compatible) {
+			printf("'fpga' image without 'compatible' property\n");
+		} else {
+			if (CONFIG_IS_ENABLED(FPGA_LOAD_SECURE))
+				flags = fpga_compatible2flag(devnum, compatible);
+		}
+
 		if (!fpga_is_partial_data(devnum, img_len)) {
 			name = "full";
 			err = fpga_loadbitstream(devnum, (char *)img_data,
 						 img_len, BIT_FULL);
 			if (err)
 				err = fpga_load(devnum, (const void *)img_data,
-						img_len, BIT_FULL, 0);
+						img_len, BIT_FULL, flags);
 		} else {
 			name = "partial";
 			err = fpga_loadbitstream(devnum, (char *)img_data,
 						 img_len, BIT_PARTIAL);
 			if (err)
 				err = fpga_load(devnum, (const void *)img_data,
-						img_len, BIT_PARTIAL, 0);
+						img_len, BIT_PARTIAL, flags);
 		}
 
 		if (err)

boot/upl_read.c

@@ -520,7 +520,7 @@ static int decode_upl_graphics(struct upl *upl, ofnode node)
 		return log_msg_ret("reg", -EINVAL);
 	}
 
-	len = decode_addr_size(upl, buf, sizeof(buf), &gra->reg);
+	len = decode_addr_size(upl, buf, size, &gra->reg);
 	if (len < 0)
 		return log_msg_ret("buf", len);
 

cmd/Kconfig

@@ -2016,7 +2016,9 @@ config CMD_PING6
 config CMD_CDP
 	bool "cdp"
 	help
-	  Perform CDP network configuration
+	  The cdp command is used to announce the U-Boot device in the network
+	  and to retrieve configuration data including the VLAN id using the
+	  proprietary Cisco Discovery Protocol (CDP).
 
 config CMD_SNTP
 	bool "sntp"
@@ -2121,6 +2123,25 @@ config CMD_WGET
 	  wget is a simple command to download kernel, or other files,
 	  from a http server over TCP.
 
+config WGET_HTTPS
+	bool "wget https"
+	depends on CMD_WGET
+	depends on PROT_TCP_LWIP
+	depends on MBEDTLS_LIB
+        select SHA256
+        select RSA
+        select ASYMMETRIC_KEY_TYPE
+        select ASYMMETRIC_PUBLIC_KEY_SUBTYPE
+        select X509_CERTIFICATE_PARSER
+        select PKCS7_MESSAGE_PARSER
+	select MBEDTLS_LIB_CRYPTO
+	select MBEDTLS_LIB_TLS
+	select RSA_VERIFY_WITH_PKEY
+	select X509_CERTIFICATE_PARSER
+	select PKCS7_MESSAGE_PARSER
+	help
+	  Enable TLS over http for wget.
+
 endif  # if CMD_NET
 
 config CMD_PXE

cmd/hash.c

@@ -25,7 +25,7 @@ static int do_hash(struct cmd_tbl *cmdtp, int flag, int argc,
 	char *s;
 	int flags = HASH_FLAG_ENV;
 
-	if (argc < (HARGS - 1))
+	if (argc < 4)
 		return CMD_RET_USAGE;
 
 #if IS_ENABLED(CONFIG_HASH_VERIFY)

cmd/net-common.c

@@ -101,9 +101,6 @@ static int do_net(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 	return cp->cmd(cmdtp, flag, argc, argv);
 }
 
-U_BOOT_CMD(
-	net, 3, 1, do_net,
-	"NET sub-system",
-	"list - list available devices\n"
-	"stats <device> - dump statistics for specified device\n"
-);
+U_BOOT_CMD(net, 3, 1, do_net, "NET sub-system",
+	   "list - list available devices\n"
+	   "stats <device> - dump statistics for specified device\n");

cmd/net-lwip.c

@@ -5,41 +5,31 @@
 #include <net.h>
 
 #if defined(CONFIG_CMD_DHCP)
-U_BOOT_CMD(
-        dhcp,   3,      1,      do_dhcp,
-        "boot image via network using DHCP/TFTP protocol",
-        "[loadAddress] [[hostIPaddr:]bootfilename]"
-);
+U_BOOT_CMD(dhcp, 3, 1, do_dhcp,
+	   "boot image via network using DHCP/TFTP protocol",
+	   "[loadAddress] [[hostIPaddr:]bootfilename]");
 #endif
 
 #if defined(CONFIG_CMD_PING)
-U_BOOT_CMD(
-	ping,	2,	1,	do_ping,
-	"send ICMP ECHO_REQUEST to network host",
-	"pingAddress"
-);
+U_BOOT_CMD(ping, 2, 1, do_ping, "send ICMP ECHO_REQUEST to network host",
+	   "pingAddress");
 #endif
 
 #if defined(CONFIG_CMD_TFTPBOOT)
-U_BOOT_CMD(
-	tftpboot,	3,	0,	do_tftpb,
-	"boot image via network using TFTP protocol\n",
-	"[loadAddress] [[hostIPaddr:]bootfilename]"
-);
+U_BOOT_CMD(tftpboot, 3, 0, do_tftpb,
+	   "boot image via network using TFTP protocol\n",
+	   "[loadAddress] [[hostIPaddr:]bootfilename]");
 #endif
 
 #if defined(CONFIG_CMD_DNS)
-U_BOOT_CMD(
-	dns,	3,	1,	do_dns,
-	"lookup the IP of a hostname",
-	"hostname [envvar]"
-);
+U_BOOT_CMD(dns, 3, 1, do_dns, "lookup the IP of a hostname",
+	   "hostname [envvar]");
 #endif
 
 #if defined(CONFIG_CMD_WGET)
-U_BOOT_CMD(
-	wget,   3,      1,      do_wget,
-	"boot image via network using HTTP protocol",
-	"[loadAddress] URL"
+U_BOOT_CMD(wget, 3, 1, do_wget,
+	   "boot image via network using HTTP/HTTPS protocol",
+	   "[loadAddress] url\n"
+	   "wget [loadAddress] [host:]path"
 );
 #endif

cmd/upl.c

@@ -50,7 +50,7 @@ static int do_upl_write(struct cmd_tbl *cmdtp, int flag, int argc,
 			char *const argv[])
 {
 	struct upl s_upl, *upl = &s_upl;
-	struct unit_test_state uts;
+	struct unit_test_state uts = { 0 };
 	struct abuf buf;
 	oftree tree;
 	ulong addr;

common/Makefile

@@ -7,6 +7,7 @@
 ifndef CONFIG_XPL_BUILD
 obj-y += init/
 obj-y += main.o
+obj-y += memtop.o
 obj-y += exports.o
 obj-y += cli_getch.o cli_simple.o cli_readline.o
 obj-$(CONFIG_HUSH_OLD_PARSER) += cli_hush.o

common/memtop.c

@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Linaro Limited
+ */
+
+#include <fdt_support.h>
+#include <fdtdec.h>
+#include <memtop.h>
+
+#include <asm/types.h>
+
+#define MEM_RGN_COUNT	16
+
+struct region {
+	phys_addr_t base;
+	phys_size_t size;
+};
+
+struct mem_region {
+	struct region rgn[MEM_RGN_COUNT];
+	uint count;
+};
+
+static void add_mem_region(struct mem_region *mem_rgn, phys_addr_t base,
+			   phys_size_t size)
+{
+	long i;
+
+	for (i = mem_rgn->count; i >= 0; i--) {
+		if (i && base < mem_rgn->rgn[i - 1].base) {
+			mem_rgn->rgn[i] = mem_rgn->rgn[i - 1];
+		} else {
+			mem_rgn->rgn[i].base = base;
+			mem_rgn->rgn[i].size = size;
+			break;
+		}
+	}
+
+	mem_rgn->count++;
+}
+
+static void mem_regions_init(struct mem_region *mem)
+{
+	uint i;
+
+	mem->count = 0;
+	for (i = 0; i < MEM_RGN_COUNT; i++) {
+		mem->rgn[i].base = 0;
+		mem->rgn[i].size = 0;
+	}
+}
+
+static int fdt_add_reserved_regions(struct mem_region *free_mem,
+				    struct mem_region *reserved_mem,
+				    void *fdt_blob)
+{
+	u64 addr, size;
+	int i, total, ret;
+	int nodeoffset, subnode;
+	struct fdt_resource res;
+
+	if (fdt_check_header(fdt_blob) != 0)
+		return -1;
+
+	/* process memreserve sections */
+	total = fdt_num_mem_rsv(fdt_blob);
+	assert_noisy(total < MEM_RGN_COUNT);
+	for (i = 0; i < total; i++) {
+		if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
+			continue;
+		add_mem_region(reserved_mem, addr, size);
+	}
+
+	i = 0;
+	/* process reserved-memory */
+	nodeoffset = fdt_subnode_offset(fdt_blob, 0, "reserved-memory");
+	if (nodeoffset >= 0) {
+		subnode = fdt_first_subnode(fdt_blob, nodeoffset);
+		while (subnode >= 0) {
+			/* check if this subnode has a reg property */
+			ret = fdt_get_resource(fdt_blob, subnode, "reg", 0,
+					       &res);
+			if (!ret && fdtdec_get_is_enabled(fdt_blob, subnode)) {
+				addr = res.start;
+				size = res.end - res.start + 1;
+				assert_noisy(i < MEM_RGN_COUNT);
+				add_mem_region(reserved_mem, addr, size);
+			}
+
+			subnode = fdt_next_subnode(fdt_blob, subnode);
+			++i;
+		}
+	}
+
+	return 0;
+}
+
+static long addrs_overlap(phys_addr_t base1, phys_size_t size1,
+			  phys_addr_t base2, phys_size_t size2)
+{
+	const phys_addr_t base1_end = base1 + size1 - 1;
+	const phys_addr_t base2_end = base2 + size2 - 1;
+
+	return ((base1 <= base2_end) && (base2 <= base1_end));
+}
+
+static long region_overlap_check(struct mem_region *mem_rgn, phys_addr_t base,
+				 phys_size_t size)
+{
+	unsigned long i;
+	struct region *rgn = mem_rgn->rgn;
+
+	for (i = 0; i < mem_rgn->count; i++) {
+		phys_addr_t rgnbase = rgn[i].base;
+		phys_size_t rgnsize = rgn[i].size;
+
+		if (addrs_overlap(base, size, rgnbase, rgnsize))
+			break;
+	}
+
+	return (i < mem_rgn->count) ? i : -1;
+}
+
+static int find_ram_top(struct mem_region *free_mem,
+			struct mem_region *reserved_mem, phys_size_t size)
+{
+	long i, rgn;
+	phys_addr_t base = 0;
+	phys_addr_t res_base;
+
+	for (i = free_mem->count - 1; i >= 0; i--) {
+		phys_addr_t rgnbase = free_mem->rgn[i].base;
+		phys_size_t rgnsize = free_mem->rgn[i].size;
+
+		if (rgnsize < size)
+			continue;
+
+		base = rgnbase + rgnsize - size;
+		while (base && rgnbase <= base) {
+			rgn = region_overlap_check(reserved_mem, base, size);
+			if (rgn < 0)
+				return base;
+
+			res_base = reserved_mem->rgn[rgn].base;
+			if (res_base < size)
+				break;
+			base = res_base - size;
+		}
+	}
+
+	return 0;
+}
+
+phys_addr_t get_mem_top(phys_addr_t ram_start, phys_size_t ram_size,
+			phys_size_t size, void *fdt)
+{
+	int i;
+	struct mem_region free_mem;
+	struct mem_region reserved_mem;
+
+	mem_regions_init(&free_mem);
+	mem_regions_init(&reserved_mem);
+
+	add_mem_region(&free_mem, ram_start, ram_size);
+
+	i = fdt_add_reserved_regions(&free_mem, &reserved_mem, fdt);
+	if (i < 0)
+		return 0;
+
+	return find_ram_top(&free_mem, &reserved_mem, size);
+}

common/usb_onboard_hub.c

@@ -7,37 +7,203 @@
  * Mostly inspired by Linux kernel v6.1 onboard_usb_hub driver
  */
 
+#include <asm/gpio.h>
 #include <dm.h>
 #include <dm/device_compat.h>
+#include <i2c.h>
+#include <linux/delay.h>
 #include <power/regulator.h>
 
+#define USB5744_COMMAND_ATTACH		0x0056
+#define USB5744_COMMAND_ATTACH_LSB	0xAA
+#define USB5744_CONFIG_REG_ACCESS	0x0037
+#define USB5744_CONFIG_REG_ACCESS_LSB	0x99
+
 struct onboard_hub {
 	struct udevice *vdd;
+	struct gpio_desc *reset_gpio;
 };
 
+struct onboard_hub_data {
+	unsigned long reset_us;
+	unsigned long power_on_delay_us;
+	int (*init)(struct udevice *dev);
+};
+
+static int usb5744_i2c_init(struct udevice *dev)
+{
+	/*
+	 *  Prevent the MCU from the putting the HUB in suspend mode through register write.
+	 *  The BYPASS_UDC_SUSPEND bit (Bit 3) of the RuntimeFlags2 register at address
+	 *  0x411D controls this aspect of the hub.
+	 *  Format to write to hub registers via SMBus- 2D 00 00 05 00 01 41 1D 08
+	 *  Byte 0: Address of slave 2D
+	 *  Byte 1: Memory address 00
+	 *  Byte 2: Memory address 00
+	 *  Byte 3: Number of bytes to write to memory
+	 *  Byte 4: Write configuration register (00)
+	 *  Byte 5: Write the number of data bytes (01- 1 data byte)
+	 *  Byte 6: LSB of register address 0x41
+	 *  Byte 7: MSB of register address 0x1D
+	 *  Byte 8: value to be written to the register
+	 */
+	u8 data_buf[8] = {0x0, 0x5, 0x0, 0x1, 0x41, 0x1D, 0x08};
+	u8 config_reg_access_buf = USB5744_CONFIG_REG_ACCESS;
+	struct udevice *i2c_bus = NULL, *i2c_dev;
+	struct ofnode_phandle_args phandle;
+	u8 buf = USB5744_COMMAND_ATTACH;
+	struct dm_i2c_chip *i2c_chip;
+	int ret, slave_addr;
+
+	ret = dev_read_phandle_with_args(dev, "i2c-bus", NULL, 0, 0, &phandle);
+	if (ret) {
+		dev_err(dev, "i2c-bus not specified\n");
+		return ret;
+	}
+
+	ret = device_get_global_by_ofnode(ofnode_get_parent(phandle.node), &i2c_bus);
+	if (ret) {
+		dev_err(dev, "Failed to get i2c node, err: %d\n", ret);
+		return ret;
+	}
+
+	ret = ofnode_read_u32(phandle.node, "reg", &slave_addr);
+	if (ret)
+		return ret;
+
+	ret = i2c_get_chip(i2c_bus, slave_addr, 1, &i2c_dev);
+	if (ret) {
+		dev_err(dev, "%s: can't find i2c chip device for addr 0x%x\n", __func__,
+			slave_addr);
+		return ret;
+	}
+
+	i2c_chip = dev_get_parent_plat(i2c_dev);
+	if (!i2c_chip) {
+		dev_err(dev, "parent platform data not found\n");
+		return -EINVAL;
+	}
+
+	i2c_chip->flags &= ~DM_I2C_CHIP_WR_ADDRESS;
+	/* SMBus write command */
+	ret = dm_i2c_write(i2c_dev, 0, (uint8_t *)&data_buf, 8);
+	if (ret) {
+		dev_err(dev, "data_buf i2c_write failed, err:%d\n", ret);
+		return ret;
+	}
+
+	/* Configuration register access command */
+	ret = dm_i2c_write(i2c_dev, USB5744_CONFIG_REG_ACCESS_LSB,
+			   &config_reg_access_buf, 2);
+	if (ret) {
+		dev_err(dev, "config_reg_access i2c_write failed, err: %d\n", ret);
+		return ret;
+	}
+
+	/* USB Attach with SMBus */
+	ret = dm_i2c_write(i2c_dev, USB5744_COMMAND_ATTACH_LSB, &buf, 2);
+	if (ret) {
+		dev_err(dev, "usb_attach i2c_write failed, err: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int usb_onboard_hub_reset(struct udevice *dev)
+{
+	struct onboard_hub_data *data =
+		(struct onboard_hub_data *)dev_get_driver_data(dev);
+	struct onboard_hub *hub = dev_get_priv(dev);
+	int ret;
+
+	hub->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_IS_OUT);
+
+	/* property is optional, don't return error! */
+	if (!hub->reset_gpio)
+		return 0;
+
+	ret = dm_gpio_set_value(hub->reset_gpio, 1);
+	if (ret)
+		return ret;
+
+	udelay(data->reset_us);
+
+	ret = dm_gpio_set_value(hub->reset_gpio, 0);
+	if (ret)
+		return ret;
+
+	udelay(data->power_on_delay_us);
+
+	return 0;
+}
+
 static int usb_onboard_hub_probe(struct udevice *dev)
 {
+	struct onboard_hub_data *data =
+		(struct onboard_hub_data *)dev_get_driver_data(dev);
 	struct onboard_hub *hub = dev_get_priv(dev);
 	int ret;
 
 	ret = device_get_supply_regulator(dev, "vdd-supply", &hub->vdd);
-	if (ret) {
+	if (ret && ret != -ENOENT) {
 		dev_err(dev, "can't get vdd-supply: %d\n", ret);
 		return ret;
 	}
 
-	ret = regulator_set_enable_if_allowed(hub->vdd, true);
-	if (ret)
-		dev_err(dev, "can't enable vdd-supply: %d\n", ret);
+	if (hub->vdd) {
+		ret = regulator_set_enable_if_allowed(hub->vdd, true);
+		if (ret && ret != -ENOSYS) {
+			dev_err(dev, "can't enable vdd-supply: %d\n", ret);
+			return ret;
+		}
+	}
 
+	ret = usb_onboard_hub_reset(dev);
+	if (ret)
+		return ret;
+
+	if (data->init) {
+		ret = data->init(dev);
+		if (ret) {
+			dev_err(dev, "onboard i2c init failed: %d\n", ret);
+			goto err;
+		}
+	}
+	return 0;
+err:
+	dm_gpio_set_value(hub->reset_gpio, 0);
 	return ret;
 }
 
+static int usb_onboard_hub_bind(struct udevice *dev)
+{
+	struct ofnode_phandle_args phandle;
+	const void *fdt = gd->fdt_blob;
+	int ret, off;
+
+	ret = dev_read_phandle_with_args(dev, "peer-hub", NULL, 0, 0, &phandle);
+	if (ret)  {
+		dev_err(dev, "peer-hub not specified\n");
+		return ret;
+	}
+
+	off = ofnode_to_offset(phandle.node);
+	ret = fdt_node_check_compatible(fdt, off, "usb424,5744");
+	if (!ret)
+		return 0;
+
+	return -ENODEV;
+}
+
 static int usb_onboard_hub_remove(struct udevice *dev)
 {
 	struct onboard_hub *hub = dev_get_priv(dev);
 	int ret;
 
+	if (hub->reset_gpio)
+		dm_gpio_free(hub->reset_gpio->dev, hub->reset_gpio);
+
 	ret = regulator_set_enable_if_allowed(hub->vdd, false);
 	if (ret)
 		dev_err(dev, "can't disable vdd-supply: %d\n", ret);
@@ -45,15 +211,34 @@ static int usb_onboard_hub_remove(struct udevice *dev)
 	return ret;
 }
 
+static const struct onboard_hub_data usb2514_data = {
+	.power_on_delay_us = 500,
+	.reset_us = 1,
+};
+
+static const struct onboard_hub_data usb5744_data = {
+	.init = usb5744_i2c_init,
+	.power_on_delay_us = 1000,
+	.reset_us = 5,
+};
+
 static const struct udevice_id usb_onboard_hub_ids[] = {
 	/* Use generic usbVID,PID dt-bindings (usb-device.yaml) */
-	{ .compatible = "usb424,2514" }, /* USB2514B USB 2.0 */
-	{ }
+	{	.compatible = "usb424,2514",	/* USB2514B USB 2.0 */
+		.data = (ulong)&usb2514_data,
+	}, {
+		.compatible = "usb424,2744",	/* USB2744 USB 2.0 */
+		.data = (ulong)&usb5744_data,
+	}, {
+		.compatible = "usb424,5744",	/* USB5744 USB 3.0 */
+		.data = (ulong)&usb5744_data,
+	}
 };
 
 U_BOOT_DRIVER(usb_onboard_hub) = {
 	.name	= "usb_onboard_hub",
 	.id	= UCLASS_USB_HUB,
+	.bind   = usb_onboard_hub_bind,
 	.probe = usb_onboard_hub_probe,
 	.remove = usb_onboard_hub_remove,
 	.of_match = usb_onboard_hub_ids,

common/xyzModem.c

@@ -280,6 +280,7 @@ xyzModem_get_hdr (void)
 	    {
 	    case SOH:
 	      xyz.total_SOH++;
+	      fallthrough;
 	    case STX:
 	      if (c == STX)
 		xyz.total_STX++;

configs/10m50_defconfig

@@ -24,15 +24,15 @@ CONFIG_CMD_CPU=y
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_RX_ETH_BUFFER=0
 CONFIG_ALTERA_PIO=y
 CONFIG_MISC=y

configs/3c120_defconfig

@@ -24,15 +24,15 @@ CONFIG_CMD_CPU=y
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_ITEST is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_VERSION_VARIABLE=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_RX_ETH_BUFFER=0
 CONFIG_ALTERA_PIO=y
 CONFIG_MISC=y

configs/CMPCPRO_defconfig

@@ -135,8 +135,8 @@ CONFIG_CMD_ASKENV=y
 CONFIG_CMD_MTD=y
 CONFIG_CMD_NAND=y
 CONFIG_CMD_TEMPERATURE=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_SLEEP is not set

configs/M5235EVB_Flash32_defconfig

@@ -24,8 +24,8 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_MII_INIT=y
 CONFIG_CMD_PING=y

configs/M5235EVB_defconfig

@@ -23,8 +23,8 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_PCI=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_MII_INIT=y
 CONFIG_CMD_PING=y

configs/M5275EVB_defconfig

@@ -23,8 +23,8 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_MII_INIT=y
 CONFIG_CMD_PING=y

configs/MPC8548CDS_36BIT_defconfig

@@ -37,8 +37,8 @@ CONFIG_CMD_I2C=y
 CONFIG_LOADS_ECHO=y
 CONFIG_SYS_LOADS_BAUD_CHANGE=y
 CONFIG_CMD_PCI=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set

configs/MPC8548CDS_defconfig

@@ -36,8 +36,8 @@ CONFIG_CMD_I2C=y
 CONFIG_LOADS_ECHO=y
 CONFIG_SYS_LOADS_BAUD_CHANGE=y
 CONFIG_CMD_PCI=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 # CONFIG_CMD_HASH is not set

configs/P1010RDB-PA_36BIT_NAND_defconfig

@@ -5,7 +5,6 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xD0000000
@@ -13,6 +12,7 @@ CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y

configs/P1010RDB-PA_36BIT_SDCARD_defconfig

@@ -7,11 +7,11 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig

@@ -8,10 +8,10 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y

configs/P1010RDB-PA_NAND_defconfig

@@ -5,7 +5,6 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xD0000000
@@ -13,6 +12,7 @@ CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y

configs/P1010RDB-PA_SDCARD_defconfig

@@ -7,11 +7,11 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/P1010RDB-PA_SPIFLASH_defconfig

@@ -8,10 +8,10 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y

configs/P1010RDB-PB_36BIT_NAND_defconfig

@@ -5,7 +5,6 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xD0000000
@@ -13,6 +12,7 @@ CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y

configs/P1010RDB-PB_36BIT_SDCARD_defconfig

@@ -7,11 +7,11 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig

@@ -8,10 +8,10 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y

configs/P1010RDB-PB_NAND_defconfig

@@ -5,7 +5,6 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xD0000000
@@ -13,6 +12,7 @@ CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y

configs/P1010RDB-PB_SDCARD_defconfig

@@ -7,11 +7,11 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/P1010RDB-PB_SPIFLASH_defconfig

@@ -8,10 +8,10 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
-CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xD0000000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y

configs/P1020RDB-PC_36BIT_NAND_defconfig

@@ -5,13 +5,13 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xF8F80000
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y

configs/P1020RDB-PC_36BIT_SDCARD_defconfig

@@ -7,10 +7,10 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig

@@ -8,9 +8,9 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y

configs/P1020RDB-PC_NAND_defconfig

@@ -5,13 +5,13 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xF8F80000
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y

configs/P1020RDB-PC_SDCARD_defconfig

@@ -7,10 +7,10 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/P1020RDB-PC_SPIFLASH_defconfig

@@ -8,9 +8,9 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y

configs/P1020RDB-PD_NAND_defconfig

@@ -5,13 +5,13 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xF8F80000
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y

configs/P1020RDB-PD_SDCARD_defconfig

@@ -7,10 +7,10 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/P1020RDB-PD_SPIFLASH_defconfig

@@ -8,9 +8,9 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y

configs/P2020RDB-PC_36BIT_NAND_defconfig

@@ -5,13 +5,13 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xF8F80000
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y

configs/P2020RDB-PC_36BIT_SDCARD_defconfig

@@ -7,10 +7,10 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig

@@ -8,9 +8,9 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y

configs/P2020RDB-PC_NAND_defconfig

@@ -5,13 +5,13 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
-CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_TPL_TEXT_BASE=0xF8F80000
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_TPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xFF800000
 CONFIG_SPL=y
 CONFIG_TPL_MAX_SIZE=0x20000
 CONFIG_MPC85xx=y

configs/P2020RDB-PC_SDCARD_defconfig

@@ -7,10 +7,10 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/P2020RDB-PC_SPIFLASH_defconfig

@@ -8,9 +8,9 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
-CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
+CONFIG_SPL_TEXT_BASE=0xf8f80000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y

configs/SBx81LIFKW_defconfig

@@ -27,11 +27,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_DM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_NTPSERVER=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
 CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
 CONFIG_DOS_PARTITION=y
 CONFIG_OF_CONTROL=y
@@ -40,8 +40,8 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_SPI_MAX_HZ=20000000
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETCONSOLE=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y

configs/SBx81LIFXCAT_defconfig

@@ -27,11 +27,11 @@ CONFIG_HUSH_PARSER=y
 CONFIG_CMD_DM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_NTPSERVER=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_CMD_SNTP=y
 # CONFIG_CMD_LED is not set
 CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
 CONFIG_DOS_PARTITION=y

configs/T1024RDB_NAND_defconfig

@@ -7,10 +7,10 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/T1024RDB_SDCARD_defconfig

@@ -7,11 +7,11 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/T1024RDB_SPIFLASH_defconfig

@@ -8,10 +8,10 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y

configs/T1042D4RDB_NAND_defconfig

@@ -6,10 +6,10 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x180000
 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/T1042D4RDB_SDCARD_defconfig

@@ -6,11 +6,11 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/T1042D4RDB_SPIFLASH_defconfig

@@ -7,10 +7,10 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y

configs/T2080QDS_NAND_defconfig

@@ -6,10 +6,10 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x140000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/T2080QDS_SDCARD_defconfig

@@ -6,11 +6,11 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/T2080QDS_SPIFLASH_defconfig

@@ -7,10 +7,10 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y

configs/T2080RDB_NAND_defconfig

@@ -6,10 +6,10 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/T2080RDB_SDCARD_defconfig

@@ -6,11 +6,11 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/T2080RDB_SPIFLASH_defconfig

@@ -7,10 +7,10 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y

configs/T2080RDB_revD_NAND_defconfig

@@ -6,10 +6,10 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/T2080RDB_revD_SDCARD_defconfig

@@ -6,11 +6,11 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/T2080RDB_revD_SPIFLASH_defconfig

@@ -7,10 +7,10 @@ CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y

configs/T4240RDB_SDCARD_defconfig

@@ -6,11 +6,11 @@ CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_TEXT_BASE=0xFFFD8000
 CONFIG_SPL=y
 CONFIG_MPC85xx=y
 CONFIG_SYS_INIT_RAM_LOCK=y

configs/ae350_rv32_falcon_xip_defconfig

@@ -6,9 +6,9 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000
 CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
-CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SYS_MONITOR_LEN=786432
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000
+CONFIG_SPL_TEXT_BASE=0x80000000
 CONFIG_SPL_BSS_START_ADDR=0x400000
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_SYS_LOAD_ADDR=0x100000