mirror of
https://github.com/u-boot/u-boot.git
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4de127a44a
Use RTC available in HW on Kria SOM without using emulation that's why configure it properly and disable emulated one. Power on reset value of RTC Calibration register without battery backup is not matching with crystal frequency which leads to RTC time drift. That's why write CALIB_WRITE register with crystal frequency (0x7FFF). There is also an option to write zero so that Linux will set default value (0x7FFF) in driver probe but calibration 0 is not permited by DT schema. Co-developed-by: Srinivas Goud <srinivas.goud@amd.com> Signed-off-by: Srinivas Goud <srinivas.goud@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9b684faeec85381b9b8fe796aaebc2ee79f17b8e.1729663761.git.michal.simek@amd.com
482 lines
9.9 KiB
Text
482 lines
9.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A
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*
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* (C) Copyright 2020 - 2021, Xilinx, Inc.
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* (C) Copyright 2023, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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/ {
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model = "ZynqMP SM-K26 Rev2/1/B/A";
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compatible = "xlnx,zynqmp-sm-k26-rev2",
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"xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
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"xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
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"xlnx,zynqmp";
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhci0;
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mmc1 = &sdhci1;
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nvmem0 = &eeprom;
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nvmem1 = &eeprom_cc;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &dcc;
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spi0 = &qspi;
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spi1 = &spi0;
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spi2 = &spi1;
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usb0 = &usb0;
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usb1 = &usb1;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial1:115200n8";
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};
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memory@0 {
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device_type = "memory"; /* 4GB */
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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pmu_region: pmu@7ff00000 {
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reg = <0x0 0x7ff00000 0x0 0x100000>;
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no-map;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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key-fwuen {
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label = "fwuen";
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gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_MISC>;
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wakeup-source;
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autorepeat;
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};
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};
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leds {
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compatible = "gpio-leds";
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ds35-led {
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label = "heartbeat";
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gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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ds36-led {
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label = "vbus_det";
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gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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};
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ams {
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compatible = "iio-hwmon";
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io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
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<&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
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<&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
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<&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
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<&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
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<&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
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<&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
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<&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
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<&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
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<&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
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};
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pwm-fan {
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compatible = "pwm-fan";
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status = "okay";
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pwms = <&ttc0 2 40000 1>;
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};
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};
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&modepin_gpio {
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label = "modepin";
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};
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&ttc0 {
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status = "okay";
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#pwm-cells = <3>;
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};
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&uart1 { /* MIO36/MIO37 */
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status = "okay";
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};
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&pinctrl0 {
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status = "okay";
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pinctrl_sdhci0_default: sdhci0-default {
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conf {
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groups = "sdio0_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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};
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mux {
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groups = "sdio0_0_grp";
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function = "sdio0";
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};
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};
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};
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&qspi { /* MIO 0-5 - U143 */
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status = "okay";
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spi_flash: flash@0 { /* MT25QU512A */
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compatible = "jedec,spi-nor"; /* 64MB */
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reg = <0>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <40000000>; /* 40MHz */
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Image Selector";
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reg = <0x0 0x80000>; /* 512KB */
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read-only;
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lock;
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};
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partition@80000 {
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label = "Image Selector Golden";
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reg = <0x80000 0x80000>; /* 512KB */
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read-only;
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lock;
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};
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partition@100000 {
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label = "Persistent Register";
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reg = <0x100000 0x20000>; /* 128KB */
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};
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partition@120000 {
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label = "Persistent Register Backup";
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reg = <0x120000 0x20000>; /* 128KB */
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};
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partition@140000 {
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label = "Open_1";
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reg = <0x140000 0xC0000>; /* 768KB */
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};
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partition@200000 {
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label = "Image A (FSBL, PMU, ATF, U-Boot)";
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reg = <0x200000 0xD00000>; /* 13MB */
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};
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partition@f00000 {
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label = "ImgSel Image A Catch";
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reg = <0xF00000 0x80000>; /* 512KB */
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read-only;
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lock;
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};
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partition@f80000 {
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label = "Image B (FSBL, PMU, ATF, U-Boot)";
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reg = <0xF80000 0xD00000>; /* 13MB */
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};
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partition@1c80000 {
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label = "ImgSel Image B Catch";
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reg = <0x1C80000 0x80000>; /* 512KB */
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read-only;
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lock;
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};
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partition@1d00000 {
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label = "Open_2";
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reg = <0x1D00000 0x100000>; /* 1MB */
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};
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partition@1e00000 {
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label = "Recovery Image";
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reg = <0x1E00000 0x200000>; /* 2MB */
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read-only;
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lock;
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};
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partition@2000000 {
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label = "Recovery Image Backup";
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reg = <0x2000000 0x200000>; /* 2MB */
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read-only;
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lock;
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};
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partition@2200000 {
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label = "U-Boot storage variables";
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reg = <0x2200000 0x20000>; /* 128KB */
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};
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partition@2220000 {
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label = "U-Boot storage variables backup";
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reg = <0x2220000 0x20000>; /* 128KB */
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};
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partition@2240000 {
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label = "SHA256";
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reg = <0x2240000 0x40000>; /* 256B but 256KB sector */
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read-only;
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lock;
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};
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partition@2280000 {
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label = "Secure OS Storage";
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reg = <0x2280000 0x20000>; /* 128KB */
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};
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partition@22a0000 {
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label = "User";
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reg = <0x22a0000 0x1d60000>; /* 29.375 MB */
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};
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};
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};
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};
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&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhci0_default>;
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non-removable;
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disable-wp;
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no-sd;
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no-sdio;
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cap-mmc-hw-reset;
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bus-width = <8>;
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xlnx,mio-bank = <0>;
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assigned-clock-rates = <187498123>;
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};
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&spi1 { /* MIO6, 9-11 */
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status = "okay";
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label = "TPM";
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num-cs = <1>;
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tpm@0 { /* slm9670 - U144 */
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compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
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reg = <0>;
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spi-max-frequency = <18500000>;
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};
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};
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&i2c1 {
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status = "okay";
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bootph-all;
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clock-frequency = <400000>;
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scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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eeprom: eeprom@50 { /* u46 - also at address 0x58 */
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bootph-all;
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compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
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reg = <0x50>;
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/* WP pin EE_WP_EN connected to slg7x644092@68 */
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};
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eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
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bootph-all;
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compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
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reg = <0x51>;
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};
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/* da9062@30 - u170 - also at address 0x31 */
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/* da9131@33 - u167 */
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da9131: pmic@33 {
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compatible = "dlg,da9131";
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reg = <0x33>;
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regulators {
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da9131_buck1: buck1 {
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regulator-name = "da9131_buck1";
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regulator-boot-on;
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regulator-always-on;
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};
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da9131_buck2: buck2 {
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regulator-name = "da9131_buck2";
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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/* da9130@32 - u166 */
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da9130: pmic@32 {
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compatible = "dlg,da9130";
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reg = <0x32>;
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regulators {
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da9130_buck1: buck1 {
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regulator-name = "da9130_buck1";
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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/* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
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/*
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* stdp4320 - u27 FW has below two issues to be fixed in next board revision.
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* Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
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* Address conflict with slg7x644091@70 making both the devices NOT accessible.
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* With the FW fix, stdp4320 should respond to address 0x73 only.
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*/
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/* slg7x644092@68 - u169 */
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/* Also connected via JA1C as C23/C24 */
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};
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&gpio {
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status = "okay";
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gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
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"QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
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"SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
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"EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
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"EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
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"I2C1_SDA", "", "", "", "", /* 25 - 29 */
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"", "", "", "", "", /* 30 - 34 */
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"", "", "", "", "", /* 35 - 39 */
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"", "", "", "", "", /* 40 - 44 */
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"", "", "", "", "", /* 45 - 49 */
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"", "", "", "", "", /* 50 - 54 */
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"", "", "", "", "", /* 55 - 59 */
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"", "", "", "", "", /* 60 - 64 */
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"", "", "", "", "", /* 65 - 69 */
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"", "", "", "", "", /* 70 - 74 */
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"", "", "", /* 75 - 77, MIO end and EMIO start */
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"", "", /* 78 - 79 */
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"", "", "", "", "", /* 80 - 84 */
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"", "", "", "", "", /* 85 - 89 */
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"", "", "", "", "", /* 90 - 94 */
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"", "", "", "", "", /* 95 - 99 */
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"", "", "", "", "", /* 100 - 104 */
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"", "", "", "", "", /* 105 - 109 */
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"", "", "", "", "", /* 110 - 114 */
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"", "", "", "", "", /* 115 - 119 */
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"", "", "", "", "", /* 120 - 124 */
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"", "", "", "", "", /* 125 - 129 */
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"", "", "", "", "", /* 130 - 134 */
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"", "", "", "", "", /* 135 - 139 */
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"", "", "", "", "", /* 140 - 144 */
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"", "", "", "", "", /* 145 - 149 */
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"", "", "", "", "", /* 150 - 154 */
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"", "", "", "", "", /* 155 - 159 */
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"", "", "", "", "", /* 160 - 164 */
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"", "", "", "", "", /* 165 - 169 */
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"", "", "", ""; /* 170 - 173 */
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};
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&xilinx_ams {
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status = "okay";
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};
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&ams_ps {
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status = "okay";
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};
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&ams_pl {
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status = "okay";
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};
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&zynqmp_dpsub {
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status = "okay";
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};
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&rtc {
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status = "okay";
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calibration = <0x7fff>;
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};
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&lpd_dma_chan1 {
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status = "okay";
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};
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&lpd_dma_chan2 {
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status = "okay";
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};
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&lpd_dma_chan3 {
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status = "okay";
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};
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&lpd_dma_chan4 {
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status = "okay";
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};
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&lpd_dma_chan5 {
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status = "okay";
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};
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&lpd_dma_chan6 {
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status = "okay";
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};
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&lpd_dma_chan7 {
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status = "okay";
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};
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&lpd_dma_chan8 {
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status = "okay";
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};
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&fpd_dma_chan1 {
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status = "okay";
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};
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&fpd_dma_chan2 {
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status = "okay";
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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};
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&gpu {
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status = "okay";
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};
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&lpd_watchdog {
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status = "okay";
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};
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&watchdog0 {
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status = "okay";
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};
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&cpu_opp_table {
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opp00 {
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opp-hz = /bits/ 64 <1333333333>;
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};
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opp01 {
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opp-hz = /bits/ 64 <666666666>;
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};
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opp02 {
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opp-hz = /bits/ 64 <444444444>;
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};
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opp03 {
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opp-hz = /bits/ 64 <333333333>;
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};
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};
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