Merge branch 'nand-next' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next

CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/25178 This merge request add support for cadence raw nand driver for agilex board and add a fix to meson driver.
2025-04-22 04:44:46 +00:00 · 2025-03-17 10:18:18 -06:00 · 2025-03-17 10:18:18 -06:00 · 4101b56d0b
commit 4101b56d0b
parent 0e1fc465fe 448d27f6ad
16 changed files with 3294 additions and 38 deletions
--- a/arch/arm/dts/socfpga_agilex5.dtsi
+++ b/arch/arm/dts/socfpga_agilex5.dtsi
@ -331,6 +331,20 @@
 			status = "disabled";
 		};

+		nand: nand@10b80000 {
+			compatible = "cdns,nand";
+			reg = <0x10b80000 0x10000>,
+				<0x10840000 0x1000>;
+			reg-names = "reg", "sdma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0 97 4>;
+			clocks = <&clkmgr AGILEX5_NAND_CLK>;
+			resets = <&rst NAND_RESET>, <&rst COMBOPHY_RESET>;
+			cdns,board-delay-ps = <4830>;
+			status = "disabled";
+		};
+
 		ocram: sram@00000000 {
 			compatible = "mmio-sram";
 			reg = <0x00000000 0x200000>;
--- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@ -69,6 +69,10 @@
 	/delete-property/ cdns,read-delay;
 };

+&flash1 {
+	bootph-all;
+};
+
 &i3c0 {
 	bootph-all;
 };
@ -130,6 +134,10 @@
 	status = "okay";
 };

+&nand {
+	bootph-all;
+};
+
 &timer0 {
 	bootph-all;
 };
--- a/arch/arm/dts/socfpga_agilex5_socdk.dts
+++ b/arch/arm/dts/socfpga_agilex5_socdk.dts
@ -165,3 +165,22 @@
 		};
 	};
 };
+
+&nand {
+	status = "okay";
+
+	flash1: flash@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "u-boot";
+			reg = <0 0x200000>;
+		};
+		partition@200000 {
+			label = "root";
+			reg = <0x200000 0x3fe00000>;
+		};
+	};
+};
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@ -110,11 +110,6 @@ int power_init_board(void)
 		pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4);
 	}

-	if (IS_ENABLED(CONFIG_IMX93_EVK_LPDDR4X)) {
-		/* Set VDDQ to 1.1V from buck2 */
-		pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28);
-	}
-
 	/* set standby voltage to 0.65v */
 	if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
 		pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
--- a/board/intel/agilex5-socdk/MAINTAINERS
+++ b/board/intel/agilex5-socdk/MAINTAINERS
@ -2,7 +2,9 @@ SOCFPGA BOARD
 M:	Tien Fong Chee <tien.fong.chee@intel.com>
 M:	Teik Heng Chong <teik.heng.chong@intel.com>
 M:	Jit Loon Lim <jit.loon.lim@intel.com>
+M:	Dinesh Maniyam <dinesh.maniyam@intel.com>
 S:	Maintained
 F:	board/intel/agilex5-socdk/
 F:	include/configs/socfpga_agilex5_socdk.h
 F:	configs/socfpga_agilex5_defconfig
+F:	configs/socfpga_agilex5_nand2_defconfig
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@ -193,6 +193,21 @@ static const struct rpi_model rpi_models_new_scheme[] = {
 		DTB_DIR "bcm2712-rpi-5-b.dtb",
 		true,
 	},
+	[0x18] = {
+		"Compute Module 5",
+		DTB_DIR "bcm2712-rpi-cm5-cm5io.dtb",
+		true,
+	},
+	[0x19] = {
+		"500",
+		DTB_DIR "bcm2712-rpi-500.dtb",
+		true,
+	},
+	[0x1A] = {
+		"Compute Module 5 Lite",
+		DTB_DIR "bcm2712-rpi-cm5l-cm5io.dtb",
+		true,
+	},
 };

 static const struct rpi_model rpi_models_old_scheme[] = {
@ -579,8 +594,14 @@ void  update_fdt_from_fw(void *fdt, void *fw_fdt)
 	/* kernel address randomisation seed as provided by the firmware */
 	copy_property(fdt, fw_fdt, "/chosen", "kaslr-seed");

+	/* warnings from the firmware (if any) */
+	copy_property(fdt, fw_fdt, "/chosen", "user-warnings");
+
 	/* address of the PHY device as provided by the firmware  */
 	copy_property(fdt, fw_fdt, "ethernet0/mdio@e14/ethernet-phy@1", "reg");
+
+	/* Bluetooth device address as provided by the firmware */
+	copy_property(fdt, fw_fdt, "/soc/serial@7e201000/bluetooth", "local-bd-address");
 }

 int ft_board_setup(void *blob, struct bd_info *bd)
@ -589,11 +610,13 @@ int ft_board_setup(void *blob, struct bd_info *bd)

 	update_fdt_from_fw(blob, (void *)fw_dtb_pointer);

-	node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer");
-	if (node < 0)
-		fdt_simplefb_add_node(blob);
-	else
-		fdt_simplefb_enable_and_mem_rsv(blob);
+	if (CONFIG_IS_ENABLED(FDT_SIMPLEFB)) {
+		node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer");
+		if (node < 0)
+			fdt_simplefb_add_node(blob);
+		else
+			fdt_simplefb_enable_and_mem_rsv(blob);
+	}

 #ifdef CONFIG_EFI_LOADER
 	/* Reserve the spin table */
--- a/configs/socfpga_agilex5_nand2_defconfig
+++ b/configs/socfpga_agilex5_nand2_defconfig
@ -0,0 +1,31 @@
+#include <configs/socfpga_agilex5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk"
+CONFIG_BOOTARGS="earlycon panic=-1 root=${nandroot} rw rootwait rootfstype=ubifs ubi.mtd=1"
+CONFIG_TARGET_SOCFPGA_AGILEX5_NAND2=y
+CONFIG_PHY_CADENCE_COMBOPHY=n
+CONFIG_SPL_PHY_CADENCE_COMBOPHY=n
+# CONFIG_MMC_DW is not set
+CONFIG_SPL_MTD=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_NAND_LOCK_UNLOCK=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_MTDIDS_DEFAULT="nand0=10b80000.nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=10b80000.nand.0:2m(u-boot),-(root)"
+CONFIG_CMD_UBIFS=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x0
+CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000
+CONFIG_UBI_SILENCE_MSG=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_CADENCE=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_NAND_CADENCE=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
+CONFIG_SYS_NAND_PAGE_SIZE=0x800
--- a/doc/device-tree-bindings/mtd/cadence,nand.yaml
+++ b/doc/device-tree-bindings/mtd/cadence,nand.yaml
@ -0,0 +1,98 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/cadence,nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence NAND controller
+
+maintainers:
+  - Dinesh Maniyam <dinesh.maniyam@intel.com>
+
+properties:
+  compatible:
+    enum:
+      - cdns,nand
+
+  reg-names:
+    description: |
+      There are two register regions:
+        reg:  register interface
+        sdma: host data/command interface
+    items:
+      - const: reg
+      - const: sdma
+
+  reg:
+    minItems: 2
+    maxItems: 2
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    description: |
+      There is one controller core clock
+    maxItems: 1
+
+  resets:
+    description: |
+      There are two resets:
+        controller core reset
+        combo-phy register reset
+    minItems: 1
+    maxItems: 2
+
+  cdns,board-delay-ps:
+     description: |
+        Estimated Board delay. The value includes the total
+        round trip delay for the signals and is used for deciding on values
+        associated with data read capture. The example formula for SDR mode is
+        the following:
+        board delay = RE#PAD delay + PCB trace to device + PCB trace from device
+        + DQ PAD delay
+     enum:
+       - 4830
+
+patternProperties:
+  "^nand@[a-f0-9]$":
+    type: object
+    properties:
+      compatible:
+        const: cdns,nand
+
+      reg:
+        maxItems: 1
+
+      label:
+        maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - cdns,board-delay-ps
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    nand-controller@60000000 {
+        compatible = "cdns,nand";
+        reg = <0x60000000 0x10000>, <0x80000000 0x1000>;
+        reg-names = "reg", "sdma";
+        #address-cells = <1>;
+        #size-cells = <0>;
+        clocks = <&clk>;
+        cdns,board-delay-ps = <4830>;
+        interrupts = <2 0>;
+        nand@0 {
+            label = "nand-0";
+            reg = <0>;
+        };
+        nand@1 {
+            label = "nand-1";
+            reg = <1>;
+        };
+    };
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@ -190,6 +190,21 @@ config SPL_NAND_LOAD
 	def_bool y
 	depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT

+config NAND_CADENCE
+	bool "Support Cadence NAND controller as a DT device"
+	depends on OF_CONTROL && DM_MTD
+	select SYS_NAND_SELF_INIT
+	select SPL_SYS_NAND_SELF_INIT
+	select SPL_NAND_BASE
+	select SPL_NAND_DRIVERS
+	select SPL_NAND_IDENT
+	select SPL_NAND_INIT
+	select SPL_NAND_ECC
+	imply CMD_NAND
+	help
+	  Enable the driver for NAND flash on platforms using a Cadence NAND
+	  controller as a DT device.
+
 config NAND_DENALI
 	bool
 	select SYS_NAND_SELF_INIT
@ -673,7 +688,7 @@ config SYS_NAND_PAGE_SIZE
 		SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
 		MVEBU_SPL_BOOT_DEVICE_NAND || \
 		(NAND_ATMEL && SPL_NAND_SUPPORT) || \
-		SPL_GENERATE_ATMEL_PMECC_HEADER || NAND_SANDBOX
+		SPL_GENERATE_ATMEL_PMECC_HEADER || NAND_SANDBOX || NAND_CADENCE
 	depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
 	help
 	  Number of data bytes in one page for the NAND chip on the
@ -775,6 +790,13 @@ config SPL_NAND_AM33XX_BCH
 	  so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
 	  SPL-NAND driver with software ECC correction support.

+config SPL_NAND_CADENCE
+	bool "Support Cadence NAND controller for SPL"
+	depends on SPL_NAND_SUPPORT
+	help
+	  This is a small implementation of the Cadence NAND controller
+	  for use on SPL.
+
 config SPL_NAND_DENALI
 	bool "Support Denali NAND controller for SPL"
 	depends on SPL_NAND_SUPPORT
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@ -10,6 +10,7 @@ NORMAL_DRIVERS=y
 endif

 obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
+obj-$(CONFIG_SPL_NAND_CADENCE) += cadence_spl.o
 obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o
 obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
 obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
@ -51,6 +52,7 @@ obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
 obj-$(CONFIG_DM_NAND_ATMEL) += atmel/
 obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o
 obj-$(CONFIG_NAND_BRCMNAND) += brcmnand/
+obj-$(CONFIG_NAND_CADENCE) += cadence_nand.o
 obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
 obj-$(CONFIG_NAND_DENALI) += denali.o
 obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o
--- a/drivers/mtd/nand/raw/cadence_nand.c
+++ b/drivers/mtd/nand/raw/cadence_nand.c
--- a/drivers/mtd/nand/raw/cadence_spl.c
+++ b/drivers/mtd/nand/raw/cadence_spl.c
@ -0,0 +1,59 @@
+// SPDX-License-Identifier:     GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#include <cadence-nand.h>
+#include <dm.h>
+#include <hang.h>
+#include <nand.h>
+#include <system-constants.h>
+
+/* Unselect after operation */
+void nand_deselect(void)
+{
+	struct mtd_info *mtd;
+	struct nand_chip *chip;
+
+	mtd = get_nand_dev_by_index(nand_curr_device);
+	if (!mtd)
+		hang();
+	chip = mtd_to_nand(mtd);
+
+	if (chip->select_chip)
+		chip->select_chip(mtd, -1);
+}
+
+static int nand_is_bad_block(int block)
+{
+	struct mtd_info *mtd;
+	struct nand_chip *chip;
+	loff_t ofs = block * CONFIG_SYS_NAND_BLOCK_SIZE;
+
+	mtd = get_nand_dev_by_index(nand_curr_device);
+	if (!mtd)
+		hang();
+	chip = mtd_to_nand(mtd);
+
+	return chip->block_bad(mtd, ofs);
+}
+
+static int nand_read_page(int block, int page, uchar *dst)
+{
+	struct mtd_info *mtd;
+	int page_addr = block * SYS_NAND_BLOCK_PAGES + page;
+	loff_t ofs = page_addr * CONFIG_SYS_NAND_PAGE_SIZE;
+	int ret;
+	size_t len = CONFIG_SYS_NAND_PAGE_SIZE;
+
+	mtd = get_nand_dev_by_index(nand_curr_device);
+	if (!mtd)
+		hang();
+
+	ret = nand_read(mtd, ofs, &len, dst);
+	if (ret)
+		printf("nand_read failed %d\n", ret);
+
+	return ret;
+}
+#include "nand_spl_loaders.c"
--- a/drivers/mtd/nand/raw/meson_nand.c
+++ b/drivers/mtd/nand/raw/meson_nand.c
@ -618,9 +618,7 @@ static int meson_nfc_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *ch
 		memcpy(meson_chip->data_buf, buf, mtd->writesize);

 	memset(meson_chip->info_buf, 0, chip->ecc.steps * PER_INFO_BYTE);
-
-	if (oob_required)
-		meson_nfc_set_user_byte(chip, chip->oob_poi);
+	meson_nfc_set_user_byte(chip, chip->oob_poi);

 	return meson_nfc_write_page_sub(chip, page, false);
 }
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@ -306,6 +306,35 @@ void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 	ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
 }

+/*
+ * nand_bbm_get_next_page - Get the next page for bad block markers
+ * @chip: The NAND chip
+ * @page: First page to start checking for bad block marker usage
+ *
+ * Returns an integer that corresponds to the page offset within a block, for
+ * a page that is used to store bad block markers. If no more pages are
+ * available, -EINVAL is returned.
+ */
+int nand_bbm_get_next_page(struct nand_chip *chip, int page)
+{
+	struct mtd_info *mtd = nand_to_mtd(chip);
+	int last_page = ((mtd->erasesize - mtd->writesize) >>
+			 chip->page_shift) & chip->pagemask;
+	unsigned int bbm_flags = NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE
+		| NAND_BBM_LASTPAGE;
+
+	if (page == 0 && !(chip->options & bbm_flags))
+		return 0;
+	if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE)
+		return 0;
+	if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE)
+		return 1;
+	if (page <= last_page && chip->options & NAND_BBM_LASTPAGE)
+		return last_page;
+
+	return -EINVAL;
+}
+
 /**
 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 * @mtd: MTD device structure
@ -315,40 +344,32 @@ void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 */
 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
 {
-	int page, res = 0, i = 0;
 	struct nand_chip *chip = mtd_to_nand(mtd);
-	u16 bad;
+	int first_page, page_offset;
+	int res;
+	u8 bad;

-	if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
-		ofs += mtd->erasesize - mtd->writesize;
+	first_page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+	page_offset = nand_bbm_get_next_page(chip, 0);

-	page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+	while (page_offset >= 0) {
+		res = chip->ecc.read_oob(mtd, chip, first_page + page_offset);
+		if (res < 0)
+			return res;

-	do {
-		if (chip->options & NAND_BUSWIDTH_16) {
-			chip->cmdfunc(mtd, NAND_CMD_READOOB,
-					chip->badblockpos & 0xFE, page);
-			bad = cpu_to_le16(chip->read_word(mtd));
-			if (chip->badblockpos & 0x1)
-				bad >>= 8;
-			else
-				bad &= 0xFF;
-		} else {
-			chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
-					page);
-			bad = chip->read_byte(mtd);
-		}
+		bad = chip->oob_poi[chip->badblockpos];

 		if (likely(chip->badblockbits == 8))
 			res = bad != 0xFF;
 		else
 			res = hweight8(bad) < chip->badblockbits;
-		ofs += mtd->writesize;
-		page = (int)(ofs >> chip->page_shift) & chip->pagemask;
-		i++;
-	} while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
+		if (res)
+			return res;

-	return res;
+		page_offset = nand_bbm_get_next_page(chip, page_offset + 1);
+	}
+
+	return 0;
 }

 /**
--- a/include/cadence-nand.h
+++ b/include/cadence-nand.h
@ -0,0 +1,529 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Cadence NAND flash controller driver
+ *
+ * Copyright (C) 2019 Cadence
+ *
+ * Author: Piotr Sroka <piotrs@cadence.com>
+ *
+ */
+
+#ifndef _CADENCE_NAND_H_
+#define _CADENCE_NAND_H_
+#include <clk.h>
+#include <reset.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+
+/*
+ * HPNFC can work in 3 modes:
+ * -  PIO - can work in master or slave DMA
+ * -  CDMA - needs Master DMA for accessing command descriptors.
+ * -  Generic mode - can use only slave DMA.
+ * CDMA and PIO modes can be used to execute only base commands.
+ * CDMA and PIO modes can be used to execute only base commands.
+ * Generic mode can be used to execute any command
+ * on NAND flash memory. Driver uses CDMA mode for
+ * block erasing, page reading, page programing.
+ * Generic mode is used for executing rest of commands.
+ */
+
+#define DMA_DATA_SIZE_ALIGN 8
+
+/* Register definition. */
+/*
+ * Command register 0.
+ * Writing data to this register will initiate a new transaction
+ * of the NF controller.
+ */
+#define CMD_REG0            0x0000
+/* Command type field mask. */
+#define CMD_REG0_CT         GENMASK(31, 30)
+/* Command type CDMA. */
+#define CMD_REG0_CT_CDMA    0uL
+/* Command type generic. */
+#define CMD_REG0_CT_GEN     3uL
+/* Command thread number field mask. */
+#define CMD_REG0_TN         GENMASK(27, 24)
+
+/* Command register 2. */
+#define CMD_REG2            0x0008
+/* Command register 3. */
+#define CMD_REG3            0x000C
+/* Pointer register to select which thread status will be selected. */
+#define CMD_STATUS_PTR      0x0010
+/* Command status register for selected thread. */
+#define CMD_STATUS          0x0014
+
+/* Interrupt status register. */
+#define INTR_STATUS             0x0110
+#define INTR_STATUS_SDMA_ERR    BIT(22)
+#define INTR_STATUS_SDMA_TRIGG  BIT(21)
+#define INTR_STATUS_UNSUPP_CMD  BIT(19)
+#define INTR_STATUS_DDMA_TERR   BIT(18)
+#define INTR_STATUS_CDMA_TERR   BIT(17)
+#define INTR_STATUS_CDMA_IDL    BIT(16)
+
+/* Interrupt enable register. */
+#define INTR_ENABLE             0x0114
+#define INTR_ENABLE_INTR_EN     BIT(31)
+
+/* Controller internal state. */
+#define CTRL_STATUS             0x0118
+#define CTRL_STATUS_INIT_COMP   BIT(9)
+#define CTRL_STATUS_CTRL_BUSY   BIT(8)
+
+/* Command Engine threads state. */
+#define TRD_STATUS              0x0120
+
+/* Command Engine interrupt thread error status. */
+#define TRD_ERR_INT_STATUS      0x0128
+/* Command Engine interrupt thread error enable. */
+#define TRD_ERR_INT_STATUS_EN   0x0130
+/* Command Engine interrupt thread complete status. */
+#define TRD_COMP_INT_STATUS     0x0138
+
+/*
+ * Transfer config 0 register.
+ * Configures data transfer parameters.
+ */
+#define TRAN_CFG_0              0x0400
+/* Offset value from the beginning of the page. */
+#define TRAN_CFG_0_OFFSET       GENMASK(31, 16)
+/* Numbers of sectors to transfer within singlNF device's page. */
+#define TRAN_CFG_0_SEC_CNT      GENMASK(7, 0)
+
+/*
+ * Transfer config 1 register.
+ * Configures data transfer parameters.
+ */
+#define TRAN_CFG_1                   0x0404
+/* Size of last data sector. */
+#define TRAN_CFG_1_LAST_SEC_SIZE     GENMASK(31, 16)
+/* Size of not-last data sector. */
+#define TRAN_CFG_1_SECTOR_SIZE       GENMASK(15, 0)
+
+/* ECC engine configuration register 0. */
+#define ECC_CONFIG_0                 0x0428
+/* Correction strength. */
+#define ECC_CONFIG_0_CORR_STR        GENMASK(10, 8)
+/* Enable erased pages detection mechanism. */
+#define ECC_CONFIG_0_ERASE_DET_EN    BIT(1)
+/* Enable controller ECC check bits generation and correction. */
+#define ECC_CONFIG_0_ECC_EN          BIT(0)
+
+/* ECC engine configuration register 1. */
+#define ECC_CONFIG_1            0x042C
+
+/* Multiplane settings register. */
+#define MULTIPLANE_CFG          0x0434
+/* Cache operation settings. */
+#define CACHE_CFG               0x0438
+
+/* Transferred data block size for the slave DMA module. */
+#define SDMA_SIZE               0x0440
+
+/* Thread number associated with transferred data block
+ * for the slave DMA module.
+ */
+#define SDMA_TRD_NUM            0x0444
+/* Thread number mask. */
+#define SDMA_TRD_NUM_SDMA_TRD   GENMASK(2, 0)
+
+#define CONTROL_DATA_CTRL       0x0494
+/* Thread number mask. */
+#define CONTROL_DATA_CTRL_SIZE  GENMASK(15, 0)
+
+#define CTRL_VERSION            0x800
+#define CTRL_VERSION_REV        GENMASK(7, 0)
+
+/* Available hardware features of the controller. */
+#define CTRL_FEATURES                0x804
+/* Support for NV-DDR2/3 work mode. */
+#define CTRL_FEATURES_NVDDR_2_3      BIT(28)
+/* Support for NV-DDR work mode. */
+#define CTRL_FEATURES_NVDDR          BIT(27)
+/* Support for asynchronous work mode. */
+#define CTRL_FEATURES_ASYNC          BIT(26)
+/* Support for asynchronous work mode. */
+#define CTRL_FEATURES_N_BANKS        GENMASK(25, 24)
+/* Slave and Master DMA data width. */
+#define CTRL_FEATURES_DMA_DWITH64    BIT(21)
+/* Availability of Control Data feature.*/
+#define CTRL_FEATURES_CONTROL_DATA   BIT(10)
+
+/* BCH Engine identification register 0 - correction strengths. */
+#define BCH_CFG_0               0x838
+#define BCH_CFG_0_CORR_CAP_0    GENMASK(7, 0)
+#define BCH_CFG_0_CORR_CAP_1    GENMASK(15, 8)
+#define BCH_CFG_0_CORR_CAP_2    GENMASK(23, 16)
+#define BCH_CFG_0_CORR_CAP_3    GENMASK(31, 24)
+
+/* BCH Engine identification register 1 - correction strengths. */
+#define BCH_CFG_1               0x83C
+#define BCH_CFG_1_CORR_CAP_4    GENMASK(7, 0)
+#define BCH_CFG_1_CORR_CAP_5    GENMASK(15, 8)
+#define BCH_CFG_1_CORR_CAP_6    GENMASK(23, 16)
+#define BCH_CFG_1_CORR_CAP_7    GENMASK(31, 24)
+
+/* BCH Engine identification register 2 - sector sizes. */
+#define BCH_CFG_2               0x840
+#define BCH_CFG_2_SECT_0        GENMASK(15, 0)
+#define BCH_CFG_2_SECT_1        GENMASK(31, 16)
+
+/* BCH Engine identification register 3. */
+#define BCH_CFG_3               0x844
+#define BCH_CFG_3_METADATA_SIZE GENMASK(23, 16)
+
+/* Ready/Busy# line status. */
+#define RBN_SETINGS             0x1004
+
+/* Common settings. */
+#define COMMON_SET              0x1008
+/* 16 bit device connected to the NAND Flash interface. */
+#define COMMON_SET_DEVICE_16BIT BIT(8)
+
+/* Skip_bytes registers. */
+#define SKIP_BYTES_CONF             0x100C
+#define SKIP_BYTES_MARKER_VALUE     GENMASK(31, 16)
+#define SKIP_BYTES_NUM_OF_BYTES     GENMASK(7, 0)
+
+#define SKIP_BYTES_OFFSET           0x1010
+#define SKIP_BYTES_OFFSET_VALUE     GENMASK(23, 0)
+
+/* Timings configuration. */
+#define ASYNC_TOGGLE_TIMINGS        0x101c
+#define ASYNC_TOGGLE_TIMINGS_TRH    GENMASK(28, 24)
+#define ASYNC_TOGGLE_TIMINGS_TRP    GENMASK(20, 16)
+#define ASYNC_TOGGLE_TIMINGS_TWH    GENMASK(12, 8)
+#define ASYNC_TOGGLE_TIMINGS_TWP    GENMASK(4, 0)
+
+#define TIMINGS0                    0x1024
+#define TIMINGS0_TADL               GENMASK(31, 24)
+#define TIMINGS0_TCCS               GENMASK(23, 16)
+#define TIMINGS0_TWHR               GENMASK(15, 8)
+#define TIMINGS0_TRHW               GENMASK(7, 0)
+
+#define TIMINGS1                    0x1028
+#define TIMINGS1_TRHZ               GENMASK(31, 24)
+#define TIMINGS1_TWB                GENMASK(23, 16)
+#define TIMINGS1_TVDLY              GENMASK(7, 0)
+
+#define TIMINGS2                    0x102c
+#define TIMINGS2_TFEAT              GENMASK(25, 16)
+#define TIMINGS2_CS_HOLD_TIME       GENMASK(13, 8)
+#define TIMINGS2_CS_SETUP_TIME      GENMASK(5, 0)
+
+/* Configuration of the resynchronization of slave DLL of PHY. */
+#define DLL_PHY_CTRL                    0x1034
+#define DLL_PHY_CTRL_DLL_RST_N          BIT(24)
+#define DLL_PHY_CTRL_EXTENDED_WR_MODE   BIT(17)
+#define DLL_PHY_CTRL_EXTENDED_RD_MODE   BIT(16)
+#define DLL_PHY_CTRL_RS_HIGH_WAIT_CNT   GENMASK(11, 8)
+#define DLL_PHY_CTRL_RS_IDLE_CNT        GENMASK(7, 0)
+
+/* TODO: - Identify better way to handle PHY address */
+#define PHY_OFFSET                      0x10000
+
+/* Register controlling DQ related timing. */
+#define PHY_DQ_TIMING                   PHY_OFFSET + 0x2000
+/* Register controlling DSQ related timing.  */
+#define PHY_DQS_TIMING                  PHY_OFFSET + 0x2004
+#define PHY_DQS_TIMING_DQS_SEL_OE_END   GENMASK(3, 0)
+#define PHY_DQS_TIMING_PHONY_DQS_SEL    BIT(16)
+#define PHY_DQS_TIMING_USE_PHONY_DQS    BIT(20)
+
+/* Register controlling the gate and loopback control related timing. */
+#define PHY_GATE_LPBK_CTRL              PHY_OFFSET + 0x2008
+#define PHY_GATE_LPBK_CTRL_RDS          GENMASK(24, 19)
+
+/* Register holds the control for the master DLL logic. */
+#define PHY_DLL_MASTER_CTRL             PHY_OFFSET + 0x200C
+#define PHY_DLL_MASTER_CTRL_BYPASS_MODE BIT(23)
+
+/* Register holds the control for the slave DLL logic. */
+#define PHY_DLL_SLAVE_CTRL              PHY_OFFSET + 0x2010
+
+/* This register handles the global control settings for the PHY. */
+#define PHY_CTRL                        PHY_OFFSET + 0x2080
+#define PHY_CTRL_SDR_DQS                BIT(14)
+#define PHY_CTRL_PHONY_DQS              GENMASK(9, 4)
+
+/*
+ * This register handles the global control settings
+ * for the termination selects for reads.
+ */
+#define PHY_TSEL                PHY_OFFSET + 0x2084
+
+/* Generic command layout. */
+#define GCMD_LAY_CS             GENMASK_ULL(11, 8)
+/*
+ * This bit informs the minicotroller if it has to wait for tWB
+ * after sending the last CMD/ADDR/DATA in the sequence.
+ */
+#define GCMD_LAY_TWB            BIT_ULL(6)
+/* Type of generic instruction. */
+#define GCMD_LAY_INSTR          GENMASK_ULL(5, 0)
+
+/* Generic CMD sequence type. */
+#define GCMD_LAY_INSTR_CMD      0
+/* Generic ADDR sequence type. */
+#define GCMD_LAY_INSTR_ADDR     1
+/* Generic data transfer sequence type. */
+#define GCMD_LAY_INSTR_DATA     2
+
+/* Input part of generic command type of input is command. */
+#define GCMD_LAY_INPUT_CMD          GENMASK_ULL(23, 16)
+
+/* Generic command address sequence - address fields. */
+#define GCMD_LAY_INPUT_ADDR         GENMASK_ULL(63, 16)
+/* Generic command address sequence - address size. */
+#define GCMD_LAY_INPUT_ADDR_SIZE    GENMASK_ULL(13, 11)
+
+/* Transfer direction field of generic command data sequence. */
+#define GCMD_DIR            BIT_ULL(11)
+/* Read transfer direction of generic command data sequence. */
+#define GCMD_DIR_READ       0
+/* Write transfer direction of generic command data sequence. */
+#define GCMD_DIR_WRITE      1
+
+/* ECC enabled flag of generic command data sequence - ECC enabled. */
+#define GCMD_ECC_EN             BIT_ULL(12)
+/* Generic command data sequence - sector size. */
+#define GCMD_SECT_SIZE          GENMASK_ULL(31, 16)
+/* Generic command data sequence - sector count. */
+#define GCMD_SECT_CNT           GENMASK_ULL(39, 32)
+/* Generic command data sequence - last sector size. */
+#define GCMD_LAST_SIZE          GENMASK_ULL(55, 40)
+
+/* CDMA descriptor fields. */
+/* Erase command type of CDMA descriptor. */
+#define CDMA_CT_ERASE           0x1000
+/* Program page command type of CDMA descriptor. */
+#define CDMA_CT_WR              0x2100
+/* Read page command type of CDMA descriptor. */
+#define CDMA_CT_RD              0x2200
+
+/* Flash pointer memory shift. */
+#define CDMA_CFPTR_MEM_SHIFT    24
+/* Flash pointer memory mask. */
+#define CDMA_CFPTR_MEM          GENMASK(26, 24)
+
+/*
+ * Command DMA descriptor flags. If set causes issue interrupt after
+ * the completion of descriptor processing.
+ */
+#define CDMA_CF_INT         BIT(8)
+/*
+ * Command DMA descriptor flags - the next descriptor
+ * address field is valid and descriptor processing should continue.
+ */
+#define CDMA_CF_CONT        BIT(9)
+/* DMA master flag of command DMA descriptor. */
+#define CDMA_CF_DMA_MASTER  BIT(10)
+
+/* Operation complete status of command descriptor. */
+#define CDMA_CS_COMP        BIT(15)
+/* Operation complete status of command descriptor. */
+/* Command descriptor status - operation fail. */
+#define CDMA_CS_FAIL        BIT(14)
+/* Command descriptor status - page erased. */
+#define CDMA_CS_ERP         BIT(11)
+/* Command descriptor status - timeout occurred. */
+#define CDMA_CS_TOUT        BIT(10)
+/*
+ * Maximum amount of correction applied to one ECC sector.
+ * It is part of command descriptor status.
+ */
+#define CDMA_CS_MAXERR      GENMASK(9, 2)
+/* Command descriptor status - uncorrectable ECC error. */
+#define CDMA_CS_UNCE        BIT(1)
+/* Command descriptor status - descriptor error. */
+#define CDMA_CS_ERR         BIT(0)
+
+/* Status of operation - OK. */
+#define STAT_OK             0
+/* Status of operation - FAIL. */
+#define STAT_FAIL           2
+/* Status of operation - uncorrectable ECC error. */
+#define STAT_ECC_UNCORR     3
+/* Status of operation - page erased. */
+#define STAT_ERASED         5
+/* Status of operation - correctable ECC error. */
+#define STAT_ECC_CORR       6
+/* Status of operation - unsuspected state. */
+#define STAT_UNKNOWN        7
+/* Status of operation - operation is not completed yet. */
+#define STAT_BUSY           0xFF
+
+#define BCH_MAX_NUM_CORR_CAPS       8
+#define BCH_MAX_NUM_SECTOR_SIZES    2
+
+#define ONE_CYCLE                   1
+#define TIMEOUT_US                  1000000
+
+struct cadence_nand_timings {
+	u32 async_toggle_timings;
+	u32 timings0;
+	u32 timings1;
+	u32 timings2;
+	u32 dll_phy_ctrl;
+	u32 phy_ctrl;
+	u32 phy_dqs_timing;
+	u32 phy_gate_lpbk_ctrl;
+};
+
+/* Command DMA descriptor. */
+struct cadence_nand_cdma_desc {
+	/* Next descriptor address. */
+	u64 next_pointer;
+
+	/* Flash address is a 32-bit address comprising of BANK and ROW ADDR. */
+	u32 flash_pointer;
+	/*field appears in HPNFC version 13*/
+	u16 bank;
+	u16 rsvd0;
+
+	/* Operation the controller needs to perform. */
+	u16 command_type;
+	u16 rsvd1;
+	/* Flags for operation of this command. */
+	u16 command_flags;
+	u16 rsvd2;
+
+	/* System/host memory address required for data DMA commands. */
+	u64 memory_pointer;
+
+	/* Status of operation. */
+	u32 status;
+	u32 rsvd3;
+
+	/* Address pointer to sync buffer location. */
+	u64 sync_flag_pointer;
+
+	/* Controls the buffer sync mechanism. */
+	u32 sync_arguments;
+	u32 rsvd4;
+
+	/* Control data pointer. */
+	u64 ctrl_data_ptr;
+};
+
+/* Interrupt status. */
+struct cadence_nand_irq_status {
+	/* Thread operation complete status. */
+	u32 trd_status;
+	/* Thread operation error. */
+	u32 trd_error;
+	/* Controller status. */
+	u32 status;
+};
+
+/* Cadence NAND flash controller capabilities get from driver data. */
+struct cadence_nand_dt_devdata {
+	/* Skew value of the output signals of the NAND Flash interface. */
+	u32 if_skew;
+	/* It informs if slave DMA interface is connected to DMA engine. */
+	unsigned int has_dma:1;
+};
+
+/* Cadence NAND flash controller capabilities read from registers. */
+struct cdns_nand_caps {
+	/* Maximum number of banks supported by hardware. */
+	u8 max_banks;
+	/* Slave and Master DMA data width in bytes (4 or 8). */
+	u8 data_dma_width;
+	/* Control Data feature supported. */
+	bool data_control_supp;
+	/* Is PHY type DLL. */
+	bool is_phy_type_dll;
+};
+
+struct cadence_nand_info {
+	struct nand_hw_control controller;
+	struct udevice *dev;
+	struct reset_ctl softphy_reset;
+	struct reset_ctl nand_reset;
+	struct cadence_nand_cdma_desc *cdma_desc;
+	/* IP capability. */
+	const struct cadence_nand_dt_devdata *caps1;
+	struct cdns_nand_caps caps2;
+	u8 ctrl_rev;
+	dma_addr_t dma_cdma_desc;
+	/* command interface buffers */
+	u8 *buf;
+	u32 buf_size;
+	u8 *stat;
+	u8 cmd;
+	u32 buf_index;
+
+	u8 curr_corr_str_idx;
+
+	/* Register interface. */
+	void __iomem *reg;
+
+	struct {
+	void __iomem *virt;
+	dma_addr_t dma;
+	} io;
+
+	int irq;
+	/* Interrupts that have happened. */
+	struct cadence_nand_irq_status irq_status;
+	/* Interrupts we are waiting for. */
+	struct cadence_nand_irq_status irq_mask;
+
+	int ecc_strengths[BCH_MAX_NUM_CORR_CAPS];
+	struct nand_ecc_step_info ecc_stepinfos[BCH_MAX_NUM_SECTOR_SIZES];
+	struct nand_ecc_caps ecc_caps;
+
+	int curr_trans_type;
+
+	struct clk clk;
+	u32 nf_clk_rate;
+	/*
+	 * Estimated Board delay. The value includes the total
+	 * round trip delay for the signals and is used for deciding on values
+	 * associated with data read capture.
+	 */
+	u32 board_delay;
+
+	struct nand_chip *selected_chip;
+
+	unsigned long assigned_cs;
+	struct list_head chips;
+	u8 bch_metadata_size;
+};
+
+struct cdns_nand_chip {
+	struct cadence_nand_timings timings;
+	struct nand_chip chip;
+	u8 nsels;
+	struct list_head node;
+
+	/*
+	 * part of oob area of NAND flash memory page.
+	 * This part is available for user to read or write.
+	 */
+	u32 avail_oob_size;
+
+	/* Sector size. There are few sectors per mtd->writesize */
+	u32 sector_size;
+	u32 sector_count;
+
+	/* Offset of BBM. */
+	u8 bbm_offs;
+	/* Number of bytes reserved for BBM. */
+	u8 bbm_len;
+	/* ECC strength index. */
+	u8 corr_str_idx;
+
+	u8 cs[];
+};
+
+struct ecc_info {
+	int (*calc_ecc_bytes)(int step_size, int strength);
+	int max_step_size;
+};
+
+#endif /*_CADENCE_NAND_H_*/
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@ -131,6 +131,17 @@ void nand_wait_ready(struct mtd_info *mtd);

 #define NAND_DATA_IFACE_CHECK_ONLY	-1

+/*
+ * There are different places where the manufacturer stores the factory bad
+ * block markers.
+ *
+ * Position within the block: Each of these pages needs to be checked for a
+ * bad block marking pattern.
+ */
+#define NAND_BBM_FIRSTPAGE	BIT(24)
+#define NAND_BBM_SECONDPAGE	BIT(25)
+#define NAND_BBM_LASTPAGE	BIT(26)
+
 /*
 * Constants for ECC_MODES
 */
@ -981,6 +992,7 @@ struct nand_chip {
 	struct nand_bbt_descr *bbt_md;

 	struct nand_bbt_descr *badblock_pattern;
+	int cur_cs;

 	void *priv;