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arm: socfpga: Changed to store QSPI reference clock in kHz

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Changed to store QSPI reference clock in kHz instead of Hz in
boot scratch cold0 register for Stratix10 and Agilex.

This patch is in preparation for Intel N5X SDRAM driver
support. Reserved 4 bits for Intel N5X SDRAM driver,
and there will be 28 bits to store QSPI reference clock.
Due to limited bits, QSPI reference clock frequency is
converted to kHz from Hz.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
This commit is contained in:
Siew Chin Lim 2021-03-24 17:16:50 +08:00 • committed by Ley Foon Tan
parent 3aef59f280
commit 404a98b0a4
4 changed files with 58 additions and 11 deletions
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16
arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
View file

@ -42,7 +42,10 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_GPO 0xe4
#define SYSMGR_SOC64_GPI 0xe8
#define SYSMGR_SOC64_MPU 0xf0
/* store qspi ref clock */
/*
* Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC 64-bit
* storing qspi ref clock (kHz)
*/
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200
/* store osc1 clock freq */
#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204
@ -85,6 +88,17 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_HPS_OSC_CLK 0x1358
#define SYSMGR_SOC64_IODELAY0 0x1400
/*
* Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0
* Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit
* storing qspi ref clock (kHz)
*/
#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0)
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31)
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30)
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28))
#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28
#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)