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arm: socfpga: Move Stratix10 and Agilex clock manager common code

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Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Siew Chin Lim 2021-03-24 17:16:49 +08:00 • committed by Ley Foon Tan
parent e2ffb1da1d
commit 3aef59f280
7 changed files with 13 additions and 19 deletions

15
arch/arm/mach-socfpga/clock_manager.c
View file

@ -4,12 +4,13 @@
*/
#include <common.h>
#include <asm/arch/clock_manager.h>
#include <asm/arch/system_manager.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <command.h>
#include <init.h>
#include <wait_bit.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@ -63,6 +64,14 @@ int set_cpu_clk_info(void)
return 0;
}
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
unsigned int cm_get_qspi_controller_clk_hz(void)
{
return readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
}
#endif
#ifndef CONFIG_SPL_BUILD
static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])

6
arch/arm/mach-socfpga/clock_manager_agilex.c
View file

@ -65,12 +65,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
}
u32 cm_get_qspi_controller_clk_hz(void)
{
return readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
}
void cm_print_clock_quick_summary(void)
{
printf("MPU %10d kHz\n",

6
arch/arm/mach-socfpga/clock_manager_s10.c
View file

@ -384,12 +384,6 @@ unsigned int cm_get_l4_sp_clk_hz(void)
return clock;
}
unsigned int cm_get_qspi_controller_clk_hz(void)
{
return readl(socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
}
unsigned int cm_get_spi_controller_clk_hz(void)
{
u32 clock = cm_get_l3_main_clk_hz();

1
arch/arm/mach-socfpga/include/mach/clock_manager.h
View file

@ -12,6 +12,7 @@ phys_addr_t socfpga_get_clkmgr_addr(void);
void cm_wait_for_lock(u32 mask);
int cm_wait_for_fsm(void);
void cm_print_clock_quick_summary(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
#endif
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)

2
arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
View file

@ -70,8 +70,6 @@ int cm_basic_init(const void *blob);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned long cm_get_mpu_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
#endif /* __ASSEMBLY__ */
#define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \

1
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
View file

@ -100,7 +100,6 @@ unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
unsigned int cm_get_spi_controller_clk_hz(void);
const unsigned int cm_get_osc_clk_hz(const int osc);
const unsigned int cm_get_f2s_per_ref_clk_hz(void);

1
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
View file

@ -15,7 +15,6 @@ unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
unsigned int cm_get_spi_controller_clk_hz(void);
struct cm_config {