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arm: socfpga: Changed to store QSPI reference clock in kHz

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Changed to store QSPI reference clock in kHz instead of Hz in
boot scratch cold0 register for Stratix10 and Agilex.

This patch is in preparation for Intel N5X SDRAM driver
support. Reserved 4 bits for Intel N5X SDRAM driver,
and there will be 28 bits to store QSPI reference clock.
Due to limited bits, QSPI reference clock frequency is
converted to kHz from Hz.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
This commit is contained in:
Siew Chin Lim 2021-03-24 17:16:50 +08:00 • committed by Ley Foon Tan
parent 3aef59f280
commit 404a98b0a4
4 changed files with 58 additions and 11 deletions
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4
arch/arm/mach-socfpga/include/mach/clock_manager.h
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@ -13,6 +13,10 @@ void cm_wait_for_lock(u32 mask);
int cm_wait_for_fsm(void);
void cm_print_clock_quick_summary(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
int cm_set_qspi_controller_clk_hz(u32 clk_hz);
#endif
#endif
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)