treewide: use linux/time.h for time conversion defines

Now that we have time conversion defines from in time.h there is no need
for each driver to define their own version.

Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> #at91
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> #qcom geni
Reviewed-by: Stefan Bosch <stefan_b@posteo.net> #nanopi2
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

board/friendlyarm/nanopi2/onewire.c

@@ -11,16 +11,13 @@
 #include <asm/arch/clk.h>
 #include <asm/arch/pwm.h>
 #include <i2c.h>
+#include <linux/time.h>
 
 #include <irq_func.h>
 
 #include <asm/arch/nexell.h>
 #include <asm/arch/nx_gpio.h>
 
-#ifndef NSEC_PER_SEC
-#define NSEC_PER_SEC	1000000000L
-#endif
-
 #define SAMPLE_BPS		9600
 #define SAMPLE_IN_US	101		/* (1000000 / BPS) */
 

drivers/clk/at91/clk-main.c

@@ -17,6 +17,7 @@
 #include <linux/clk/at91_pmc.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/time.h>
 #include "pmc.h"
 
 #define UBOOT_DM_CLK_AT91_MAIN_RC		"at91-main-rc-clk"
@@ -25,7 +26,6 @@
 #define UBOOT_DM_CLK_AT91_SAM9X5_MAIN		"at91-sam9x5-main-clk"
 
 #define MOR_KEY_MASK		GENMASK(23, 16)
-#define USEC_PER_SEC		1000000UL
 #define SLOW_CLOCK_FREQ		32768
 
 #define clk_main_parent_select(s)	(((s) & \

drivers/i2c/stm32f7_i2c.c

@@ -20,6 +20,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/printk.h>
+#include <linux/time.h>
 
 /* STM32 I2C registers */
 struct stm32_i2c_regs {
@@ -121,8 +122,6 @@ struct stm32_i2c_regs {
 #define STM32_SCLH_MAX				BIT(8)
 #define STM32_SCLL_MAX				BIT(8)
 
-#define STM32_NSEC_PER_SEC			1000000000L
-
 /**
  * struct stm32_i2c_spec - private i2c specification timing
  * @rate: I2C bus speed (Hz)
@@ -591,7 +590,7 @@ static int stm32_i2c_choose_solution(u32 i2cclk,
 				     struct stm32_i2c_timings *s)
 {
 	struct stm32_i2c_timings *v;
-	u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC,
+	u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 				       setup->speed_freq);
 	u32 clk_error_prev = i2cbus;
 	u32 clk_min, clk_max;
@@ -607,8 +606,8 @@ static int stm32_i2c_choose_solution(u32 i2cclk,
 	dnf_delay = setup->dnf * i2cclk;
 
 	tsync = af_delay_min + dnf_delay + (2 * i2cclk);
-	clk_max = STM32_NSEC_PER_SEC / specs->rate_min;
+	clk_max = NSEC_PER_SEC / specs->rate_min;
-	clk_min = STM32_NSEC_PER_SEC / specs->rate_max;
+	clk_min = NSEC_PER_SEC / specs->rate_max;
 
 	/*
 	 * Among Prescaler possibilities discovered above figures out SCL Low
@@ -686,7 +685,7 @@ static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv,
 	const struct stm32_i2c_spec *specs;
 	struct stm32_i2c_timings *v, *_v;
 	struct list_head solutions;
-	u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, setup->clock_src);
+	u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, setup->clock_src);
 	int ret;
 
 	specs = get_specs(setup->speed_freq);

drivers/memory/stm32-fmc2-ebi.c

@@ -14,6 +14,7 @@
 #include <linux/err.h>
 #include <linux/iopoll.h>
 #include <linux/ioport.h>
+#include <linux/time.h>
 
 /* FMC2 Controller Registers */
 #define FMC2_BCR1			0x0
@@ -90,8 +91,6 @@
 #define FMC2_BTR_DATLAT_MAX		0xf
 #define FMC2_PCSCNTR_CSCOUNT_MAX	0xff
 
-#define FMC2_NSEC_PER_SEC		1000000000L
-
 enum stm32_fmc2_ebi_bank {
 	FMC2_EBI1 = 0,
 	FMC2_EBI2,
@@ -279,7 +278,7 @@ static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi,
 					     int cs, u32 setup)
 {
 	unsigned long hclk = clk_get_rate(&ebi->clk);
-	unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
+	unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
 
 	return DIV_ROUND_UP(setup * 1000, hclkp);
 }

drivers/mmc/octeontx_hsmmc.h

@@ -32,8 +32,6 @@
  */
 #define MMC_TIMEOUT_SHORT		20
 
-#define NSEC_PER_SEC			1000000000L
-
 #define MAX_NO_OF_TAPS			64
 
 #define EXT_CSD_POWER_CLASS		187	/* R/W */

drivers/mtd/nand/raw/atmel/nand-controller.c

@@ -64,6 +64,7 @@
 #include <linux/mfd/syscon/atmel-smc.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/mtd/mtd.h>
+#include <linux/time.h>
 #include <mach/at91_sfr.h>
 #include <nand.h>
 #include <regmap.h>
@@ -71,8 +72,6 @@
 
 #include "pmecc.h"
 
-#define NSEC_PER_SEC    1000000000L
-
 #define ATMEL_HSMC_NFC_CFG			0x0
 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)		(((x) / 4) << 24)
 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK	GENMASK(30, 24)

drivers/mtd/nand/raw/mxs_nand.c

@@ -31,6 +31,7 @@
 #include <linux/errno.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/sizes.h>
+#include <linux/time.h>
 #include <linux/types.h>
 #include <linux/math64.h>
 
@@ -52,8 +53,6 @@
 #endif
 
 #define	MXS_NAND_BCH_TIMEOUT			10000
-#define	USEC_PER_SEC				1000000
-#define	NSEC_PER_SEC				1000000000L
 
 #define TO_CYCLES(duration, period) DIV_ROUND_UP_ULL(duration, period)
 

drivers/mtd/nand/raw/octeontx_nand.c

@@ -24,6 +24,7 @@
 #include <linux/mtd/nand_bch.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/rawnand.h>
+#include <linux/time.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/types.h>
@@ -291,7 +292,6 @@ union ndf_cmd {
 #define OCTEONTX_NAND_DRIVER_NAME	"octeontx_nand"
 
 #define NDF_TIMEOUT		1000	/** Timeout in ms */
-#define USEC_PER_SEC		1000000	/** Linux compatibility */
 #ifndef NAND_MAX_CHIPS
 # define NAND_MAX_CHIPS		8	/** Linux compatibility */
 #endif

drivers/mtd/nand/raw/stm32_fmc2_nand.c

@@ -22,6 +22,7 @@
 #include <linux/ioport.h>
 #include <linux/mtd/rawnand.h>
 #include <linux/printk.h>
+#include <linux/time.h>
 
 /* Bad block marker length */
 #define FMC2_BBM_LEN			2
@@ -127,8 +128,6 @@
 #define FMC2_BCHDSR4_EBP7		GENMASK(12, 0)
 #define FMC2_BCHDSR4_EBP8		GENMASK(28, 16)
 
-#define FMC2_NSEC_PER_SEC		1000000000L
-
 #define FMC2_TIMEOUT_5S			5000000
 
 enum stm32_fmc2_ecc {
@@ -603,7 +602,7 @@ static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip,
 	struct stm32_fmc2_nand *nand = to_fmc2_nand(chip);
 	struct stm32_fmc2_timings *tims = &nand->timings;
 	unsigned long hclk = clk_get_rate(&nfc->clk);
-	unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000);
+	unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
 	unsigned long timing, tar, tclr, thiz, twait;
 	unsigned long tset_mem, tset_att, thold_mem, thold_att;
 

drivers/phy/meson-axg-mipi-dphy.c

@@ -25,6 +25,7 @@
 #include <linux/bitops.h>
 #include <linux/compat.h>
 #include <linux/bitfield.h>
+#include <linux/time.h>
 
 /* [31] soft reset for the phy.
  *		1: reset. 0: dessert the reset.
@@ -170,8 +171,6 @@
 #define MIPI_DSI_TEST_CTRL0				0x3c
 #define MIPI_DSI_TEST_CTRL1				0x40
 
-#define NSEC_PER_MSEC	1000000L
-
 struct phy_meson_axg_mipi_dphy_priv {
 	struct regmap *regmap;
 #if CONFIG_IS_ENABLED(CLK)

drivers/phy/phy-core-mipi-dphy.c

@@ -6,11 +6,10 @@
 
 #include <common.h>
 #include <div64.h>
+#include <linux/time.h>
 
 #include <phy-mipi-dphy.h>
 
-#define PSEC_PER_SEC	1000000000000LL
-
 /*
  * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
  * from the valid ranges specified in Section 6.9, Table 14, Page 41

drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c

@@ -15,6 +15,7 @@
 #include <linux/clk-provider.h>
 #include <linux/delay.h>
 #include <linux/math64.h>
+#include <linux/time.h>
 #include <phy-mipi-dphy.h>
 #include <reset.h>
 
@@ -186,8 +187,6 @@
 #define DSI_PHY_STATUS				0xb0
 #define PHY_LOCK				BIT(0)
 
-#define PSEC_PER_SEC				1000000000000LL
-
 #define msleep(a)				udelay(a * 1000)
 
 enum phy_max_rate {

drivers/pwm/pwm-aspeed.c

@@ -49,6 +49,7 @@
 #include <dm/device_compat.h>
 #include <linux/math64.h>
 #include <linux/bitfield.h>
+#include <linux/time.h>
 #include <asm/io.h>
 
 /* The channel number of Aspeed pwm controller */
@@ -77,8 +78,6 @@
 /* PWM fixed value */
 #define PWM_ASPEED_FIXED_PERIOD 0xff
 
-#define NSEC_PER_SEC			1000000000L
-
 struct aspeed_pwm_priv {
 	struct clk clk;
 	struct regmap *regmap;

drivers/pwm/pwm-at91.c

@@ -14,11 +14,11 @@
 #include <dm.h>
 #include <linux/bitops.h>
 #include <linux/io.h>
+#include <linux/time.h>
 #include <pwm.h>
 
 #define PERIOD_BITS 16
 #define PWM_MAX_PRES 10
-#define NSEC_PER_SEC 1000000000L
 
 #define PWM_ENA 0x04
 #define PWM_CHANNEL_OFFSET 0x20

drivers/pwm/pwm-cadence-ttc.c

@@ -17,6 +17,7 @@
 #include <linux/bitfield.h>
 #include <linux/math64.h>
 #include <linux/log2.h>
+#include <linux/time.h>
 #include <dm/device_compat.h>
 
 #define CLOCK_CONTROL		0
@@ -37,8 +38,6 @@
 #define COUNTER_INTERVAL_ENABLE		BIT(1)
 #define COUNTER_COUNTING_DISABLE	BIT(0)
 
-#define NSEC_PER_SEC	1000000000L
-
 #define TTC_REG(reg, channel) ((reg) + (channel) * sizeof(u32))
 #define TTC_CLOCK_CONTROL(reg, channel) \
 	TTC_REG((reg) + CLOCK_CONTROL, (channel))

drivers/pwm/pwm-meson.c

@@ -26,8 +26,7 @@
 #include <linux/math64.h>
 #include <linux/bitfield.h>
 #include <linux/clk-provider.h>
-
+#include <linux/time.h>
-#define NSEC_PER_SEC 1000000000L
 
 #define REG_PWM_A		0x0
 #define REG_PWM_B		0x4

drivers/pwm/pwm-mtk.c

@@ -12,6 +12,7 @@
 #include <div64.h>
 #include <linux/bitops.h>
 #include <linux/io.h>
+#include <linux/time.h>
 
 /* PWM registers and bits definitions */
 #define PWMCON			0x00
@@ -27,8 +28,6 @@
 #define PWM_CLK_DIV_MAX		7
 #define MAX_PWM_NUM		8
 
-#define NSEC_PER_SEC 1000000000L
-
 enum mtk_pwm_reg_ver {
 	PWM_REG_V1,
 	PWM_REG_V2,

drivers/pwm/pwm-ti-ehrpwm.c

@@ -14,8 +14,7 @@
 #include <dm/device_compat.h>
 #include <pwm.h>
 #include <asm/io.h>
-
+#include <linux/time.h>
-#define NSEC_PER_SEC			        1000000000L
 
 /* Time base module registers */
 #define TI_EHRPWM_TBCTL				0x00

drivers/serial/serial_msm_geni.c

@@ -13,14 +13,13 @@
 #include <dm.h>
 #include <errno.h>
 #include <linux/delay.h>
+#include <linux/time.h>
 #include <misc.h>
 #include <serial.h>
 
 #define UART_OVERSAMPLING	32
 #define STALE_TIMEOUT	160
 
-#define USEC_PER_SEC	1000000L
-
 /* Registers*/
 #define GENI_FORCE_DEFAULT_REG	0x20
 #define GENI_SER_M_CLK_CFG	0x48

drivers/spi/cadence_qspi.c

@@ -18,12 +18,11 @@
 #include <linux/err.h>
 #include <linux/errno.h>
 #include <linux/sizes.h>
+#include <linux/time.h>
 #include <zynqmp_firmware.h>
 #include "cadence_qspi.h"
 #include <dt-bindings/power/xlnx-versal-power.h>
 
-#define NSEC_PER_SEC			1000000000L
-
 #define CQSPI_STIG_READ			0
 #define CQSPI_STIG_WRITE		1
 #define CQSPI_READ			2

drivers/spi/fsl_dspi.c

@@ -27,9 +27,7 @@
 #include <linux/bitops.h>
 #include <linux/delay.h>
 #include <linux/printk.h>
-
+#include <linux/time.h>
-/* linux/include/time.h */
-#define NSEC_PER_SEC	1000000000L
 
 DECLARE_GLOBAL_DATA_PTR;
 

drivers/ufs/cdns-platform.c

@@ -13,11 +13,10 @@
 #include <dm/device_compat.h>
 #include <linux/bitops.h>
 #include <linux/err.h>
+#include <linux/time.h>
 
 #include "ufs.h"
 
-#define USEC_PER_SEC	1000000L
-
 #define CDNS_UFS_REG_HCLKDIV	0xFC
 #define CDNS_UFS_REG_PHY_XCFGD1	0x113C
 

drivers/usb/dwc3/core.c

@@ -31,6 +31,7 @@
 #include <linux/usb/gadget.h>
 #include <linux/bitfield.h>
 #include <linux/math64.h>
+#include <linux/time.h>
 
 #include "core.h"
 #include "gadget.h"
@@ -38,8 +39,6 @@
 
 #include "linux-compat.h"
 
-#define NSEC_PER_SEC	1000000000L
-
 static LIST_HEAD(dwc3_list);
 /* -------------------------------------------------------------------------- */
 

drivers/video/dw_mipi_dsi.c

@@ -22,6 +22,7 @@
 #include <linux/bitops.h>
 #include <linux/delay.h>
 #include <linux/iopoll.h>
+#include <linux/time.h>
 #include <video_bridge.h>
 
 #define HWVER_131			0x31333100	/* IP version 1.31 */
@@ -214,8 +215,6 @@
 #define PHY_STATUS_TIMEOUT_US		10000
 #define CMD_PKT_STATUS_TIMEOUT_US	20000
 
-#define MSEC_PER_SEC			1000
-
 struct dw_mipi_dsi {
 	struct mipi_dsi_host dsi_host;
 	struct mipi_dsi_device *device;

drivers/video/rockchip/dw_mipi_dsi_rockchip.c

@@ -30,12 +30,11 @@
 #include <asm/io.h>
 #include <dm/device-internal.h>
 #include <linux/bitops.h>
+#include <linux/time.h>
 
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/hardware.h>
 
-#define USEC_PER_SEC	1000000L
-
 /*
  * DSI wrapper registers & bit definitions
  * Note: registers are named as in the Reference Manual

drivers/video/tegra20/tegra-dsi.c

@@ -14,6 +14,7 @@
 #include <panel.h>
 #include <linux/delay.h>
 #include <linux/err.h>
+#include <linux/time.h>
 #include <power/regulator.h>
 
 #include <asm/gpio.h>
@@ -24,9 +25,6 @@
 
 #include "mipi-phy.h"
 
-#define USEC_PER_SEC	1000000L
-#define NSEC_PER_SEC	1000000000L
-
 struct tegra_dsi_priv {
 	struct mipi_dsi_host host;
 	struct mipi_dsi_device device;

drivers/watchdog/sunxi_wdt.c

@@ -9,8 +9,7 @@
 #include <wdt.h>
 #include <asm/io.h>
 #include <linux/delay.h>
-
+#include <linux/time.h>
-#define MSEC_PER_SEC		1000
 
 #define WDT_MAX_TIMEOUT		16
 #define WDT_TIMEOUT_MASK	0xf

fs/ubifs/ubifs.h

@@ -68,7 +68,6 @@ struct page {
 void iput(struct inode *inode);
 
 /* linux/include/time.h */
-#define NSEC_PER_SEC	1000000000L
 #define get_seconds()	0
 #define CURRENT_TIME_SEC	((struct timespec) { get_seconds(), 0 })