mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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4b2324042a
This corrects the MISRA violation C2012-7.2: A “u” or “U” suffix shall be applied to all integer constants that are represented in an unsigned type. Appended "U" suffix to integer constant to represent it as unsigned type. Change-Id: I76f3c5903ed21ecba4d600e879d93026fc744f6c Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
146 lines
4.6 KiB
C
146 lines
4.6 KiB
C
/*
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* Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VERSAL_DEF_H
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#define VERSAL_DEF_H
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#include <plat/arm/common/smccc_def.h>
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#include <plat/common/common_def.h>
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#define PLATFORM_MASK GENMASK(27U, 24U)
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#define PLATFORM_VERSION_MASK GENMASK(31U, 28U)
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/* number of interrupt handlers. increase as required */
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#define MAX_INTR_EL3 2U
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/* List all consoles */
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#define VERSAL_CONSOLE_ID_none 0
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#define VERSAL_CONSOLE_ID_pl011 1
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#define VERSAL_CONSOLE_ID_pl011_0 1
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#define VERSAL_CONSOLE_ID_pl011_1 2
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#define VERSAL_CONSOLE_ID_dcc 3
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#define VERSAL_CONSOLE_ID_dtb 4
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#define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE)
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/* Runtime console */
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#define RT_CONSOLE_ID_pl011 1
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#define RT_CONSOLE_ID_pl011_0 1
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#define RT_CONSOLE_ID_pl011_1 2
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#define RT_CONSOLE_ID_dcc 3
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#define RT_CONSOLE_ID_dtb 4
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#define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME)
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/* List of platforms */
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#define VERSAL_SILICON U(0)
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#define VERSAL_SPP U(1)
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#define VERSAL_EMU U(2)
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#define VERSAL_QEMU U(3)
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#define VERSAL_COSIM U(7)
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/* Firmware Image Package */
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#define VERSAL_PRIMARY_CPU 0
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/*******************************************************************************
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* memory map related constants
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******************************************************************************/
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#define DEVICE0_BASE U(0xFF000000)
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#define DEVICE0_SIZE U(0x00E00000)
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#define DEVICE1_BASE U(0xF9000000)
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#define DEVICE1_SIZE U(0x00800000)
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/*******************************************************************************
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* IRQ constants
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******************************************************************************/
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#define VERSAL_IRQ_SEC_PHY_TIMER U(29)
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#define ARM_IRQ_SEC_PHY_TIMER 29
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/*******************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define PLAT_ARM_CCI_BASE U(0xFD000000)
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#define PLAT_ARM_CCI_SIZE U(0x00100000)
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#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
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#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define VERSAL_UART0_BASE U(0xFF000000)
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#define VERSAL_UART1_BASE U(0xFF010000)
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#if CONSOLE_IS(pl011) || CONSOLE_IS(dtb)
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# define UART_BASE VERSAL_UART0_BASE
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# define UART_TYPE CONSOLE_PL011
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#elif CONSOLE_IS(pl011_1)
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# define UART_BASE VERSAL_UART1_BASE
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# define UART_TYPE CONSOLE_PL011
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#elif CONSOLE_IS(dcc)
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# define UART_BASE 0x0
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# define UART_TYPE CONSOLE_DCC
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#elif CONSOLE_IS(none)
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# define UART_TYPE CONSOLE_NONE
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#else
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# error "invalid VERSAL_CONSOLE"
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#endif
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/* Runtime console */
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#if defined(CONSOLE_RUNTIME)
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#if RT_CONSOLE_IS(pl011) || RT_CONSOLE_IS(dtb)
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# define RT_UART_BASE VERSAL_UART0_BASE
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# define RT_UART_TYPE CONSOLE_PL011
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#elif RT_CONSOLE_IS(pl011_1)
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# define RT_UART_BASE VERSAL_UART1_BASE
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# define RT_UART_TYPE CONSOLE_PL011
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#elif RT_CONSOLE_IS(dcc)
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# define RT_UART_BASE 0x0
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# define RT_UART_TYPE CONSOLE_DCC
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#else
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# error "invalid CONSOLE_RUNTIME"
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#endif
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#endif
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/*******************************************************************************
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* Platform related constants
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******************************************************************************/
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#define UART_BAUDRATE 115200
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/* Access control register defines */
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#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
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#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
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/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
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#define CRF_BASE U(0xFD1A0000)
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#define CRF_SIZE U(0x00600000)
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/* CRF registers and bitfields */
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#define CRF_RST_APU (CRF_BASE + 0X00000300)
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#define CRF_RST_APU_ACPU_RESET (1 << 0)
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#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10)
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/* IOU SCNTRS */
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#define IOU_SCNTRS_BASE U(0xFF140000)
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#define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20)
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/* APU registers and bitfields */
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#define FPD_APU_BASE 0xFD5C0000U
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#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U)
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#define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U)
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#define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U)
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#define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U)
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#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U
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#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U
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#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U
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/* PMC registers and bitfields */
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#define PMC_GLOBAL_BASE 0xF1110000U
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#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U)
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#endif /* VERSAL_DEF_H */
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