mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
ef934cd17c
Cortex-A710 erratum 2282622 is a Cat B erratum that applies to revisions r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set CPUACTLR2_EL1[0] to 1, which will force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations to other PE caches. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775101 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ic48409822536e9eacc003300036a1f0489593020
51 lines
2.3 KiB
C
51 lines
2.3 KiB
C
/*
|
|
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#ifndef CORTEX_A710_H
|
|
#define CORTEX_A710_H
|
|
|
|
#define CORTEX_A710_MIDR U(0x410FD470)
|
|
|
|
/*******************************************************************************
|
|
* CPU Extended Control register specific definitions
|
|
******************************************************************************/
|
|
#define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4
|
|
#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
|
|
|
|
/*******************************************************************************
|
|
* CPU Power Control register specific definitions
|
|
******************************************************************************/
|
|
#define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
|
#define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
|
|
|
/*******************************************************************************
|
|
* CPU Auxiliary Control register specific definitions.
|
|
******************************************************************************/
|
|
#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0
|
|
#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
|
|
#define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
|
|
|
|
/*******************************************************************************
|
|
* CPU Auxiliary Control register 2 specific definitions.
|
|
******************************************************************************/
|
|
#define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1
|
|
|
|
/*******************************************************************************
|
|
* CPU Auxiliary Control register 5 specific definitions.
|
|
******************************************************************************/
|
|
#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0
|
|
#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
|
|
#define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
|
|
|
|
/*******************************************************************************
|
|
* CPU Auxiliary Control register specific definitions.
|
|
******************************************************************************/
|
|
#define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5
|
|
#define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
|
|
#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
|
|
#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
|
|
|
|
#endif /* CORTEX_A710_H */
|