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https://github.com/ARM-software/arm-trusted-firmware.git
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e5955d7c63
As per the current code base, PM_CLOCK_SETRATE and PM_CLOCK_GETRATE APIs are not supported for the runtime operations in the firmware and the TF-A it is already returning an error when there is any request to access these APIs. So, just removing the unused code to avoid the confusion around these APIs. Also, there is no issue with the backward compatibility as these APIs were never used since implemented. Hence no need to bump up the version of the feature check API as well. Signed-off-by: Ronak Jain <ronak.jain@amd.com> Change-Id: I444f973e62cd25aae2e7f697d808210b265106ad
285 lines
7.7 KiB
C
285 lines
7.7 KiB
C
/*
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* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* Versal power management enums and defines */
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#ifndef PM_DEFS_H
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#define PM_DEFS_H
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#include "pm_node.h"
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/*********************************************************************
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* Macro definitions
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********************************************************************/
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/* State arguments of the self suspend */
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#define PM_STATE_CPU_IDLE 0x0U
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#define PM_STATE_SUSPEND_TO_RAM 0xFU
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#define MAX_LATENCY (~0U)
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#define MAX_QOS 100U
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/* Processor core device IDs */
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#define APU_DEVID(IDX) NODEID(XPM_NODECLASS_DEVICE, XPM_NODESUBCL_DEV_CORE, \
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XPM_NODETYPE_DEV_CORE_APU, (IDX))
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#define XPM_DEVID_ACPU_0 APU_DEVID(XPM_NODEIDX_DEV_ACPU_0)
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#define XPM_DEVID_ACPU_1 APU_DEVID(XPM_NODEIDX_DEV_ACPU_1)
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#define PERIPH_DEVID(IDX) NODEID((uint32_t)XPM_NODECLASS_DEVICE, \
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(uint32_t)XPM_NODESUBCL_DEV_PERIPH, \
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(uint32_t)XPM_NODETYPE_DEV_PERIPH, (IDX))
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#define PM_GET_CALLBACK_DATA 0xa01U
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#define PM_GET_TRUSTZONE_VERSION 0xa03U
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#define TF_A_PM_REGISTER_SGI 0xa04U
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/* PM API Versions */
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#define PM_API_BASE_VERSION 1U
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#define PM_API_VERSION_2 2U
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/* Loader API ids */
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#define PM_LOAD_PDI 0x701U
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#define PM_LOAD_GET_HANDOFF_PARAMS 0x70BU
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/* System shutdown macros */
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#define XPM_SHUTDOWN_TYPE_SHUTDOWN 0U
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#define XPM_SHUTDOWN_TYPE_RESET 1U
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#define XPM_SHUTDOWN_TYPE_SETSCOPE_ONLY 2U
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#define XPM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM 0U
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#define XPM_SHUTDOWN_SUBTYPE_RST_PS_ONLY 1U
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#define XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM 2U
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/*********************************************************************
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* Enum definitions
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********************************************************************/
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/*
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* ioctl id
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*/
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enum {
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IOCTL_GET_RPU_OPER_MODE = 0,
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IOCTL_SET_RPU_OPER_MODE = 1,
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IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
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IOCTL_TCM_COMB_CONFIG = 3,
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IOCTL_SET_TAPDELAY_BYPASS = 4,
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IOCTL_SET_SGMII_MODE = 5,
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IOCTL_SD_DLL_RESET = 6,
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IOCTL_SET_SD_TAPDELAY = 7,
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/* Ioctl for clock driver */
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IOCTL_SET_PLL_FRAC_MODE = 8,
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IOCTL_GET_PLL_FRAC_MODE = 9,
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IOCTL_SET_PLL_FRAC_DATA = 10,
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IOCTL_GET_PLL_FRAC_DATA = 11,
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IOCTL_WRITE_GGS = 12,
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IOCTL_READ_GGS = 13,
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IOCTL_WRITE_PGGS = 14,
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IOCTL_READ_PGGS = 15,
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/* IOCTL for ULPI reset */
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IOCTL_ULPI_RESET = 16,
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/* Set healthy bit value */
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IOCTL_SET_BOOT_HEALTH_STATUS = 17,
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IOCTL_AFI = 18,
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/* Probe counter read/write */
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IOCTL_PROBE_COUNTER_READ = 19,
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IOCTL_PROBE_COUNTER_WRITE = 20,
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IOCTL_OSPI_MUX_SELECT = 21,
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/* IOCTL for USB power request */
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IOCTL_USB_SET_STATE = 22,
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/* IOCTL to get last reset reason */
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IOCTL_GET_LAST_RESET_REASON = 23,
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/* AI engine NPI ISR clear */
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IOCTL_AIE_ISR_CLEAR = 24,
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/* Register SGI to TF-A */
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IOCTL_SET_SGI = 25,
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};
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/**
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* enum pm_pll_param - enum represents the parameters for a phase-locked loop.
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* @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL.
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* @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL.
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* @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL.
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* @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input.
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* @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode.
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* @PM_PLL_PARAM_LOCK_DLY: Lock circuit config settings for lock windowsize.
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* @PM_PLL_PARAM_LOCK_CNT: Lock circuit counter setting.
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* @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control.
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* @PM_PLL_PARAM_CP: PLL charge pump control.
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* @PM_PLL_PARAM_RES: PLL loop filter resistor control.
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* @PM_PLL_PARAM_MAX: Represents the maximum parameter value for the PLL
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*/
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enum pm_pll_param {
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PM_PLL_PARAM_DIV2,
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PM_PLL_PARAM_FBDIV,
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PM_PLL_PARAM_DATA,
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PM_PLL_PARAM_PRE_SRC,
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PM_PLL_PARAM_POST_SRC,
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PM_PLL_PARAM_LOCK_DLY,
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PM_PLL_PARAM_LOCK_CNT,
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PM_PLL_PARAM_LFHF,
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PM_PLL_PARAM_CP,
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PM_PLL_PARAM_RES,
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PM_PLL_PARAM_MAX,
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};
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enum pm_api_id {
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/* Miscellaneous API functions: */
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PM_GET_API_VERSION = 1, /* Do not change or move */
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PM_SET_CONFIGURATION,
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PM_GET_NODE_STATUS,
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PM_GET_OP_CHARACTERISTIC,
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PM_REGISTER_NOTIFIER,
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/* API for suspending of PUs: */
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PM_REQ_SUSPEND,
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PM_SELF_SUSPEND,
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PM_FORCE_POWERDOWN,
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PM_ABORT_SUSPEND,
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PM_REQ_WAKEUP,
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PM_SET_WAKEUP_SOURCE,
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PM_SYSTEM_SHUTDOWN,
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/* API for managing PM slaves: */
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PM_REQ_NODE,
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PM_RELEASE_NODE,
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PM_SET_REQUIREMENT,
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PM_SET_MAX_LATENCY,
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/* Direct control API functions: */
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PM_RESET_ASSERT,
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PM_RESET_GET_STATUS,
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PM_MMIO_WRITE,
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PM_MMIO_READ,
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PM_INIT_FINALIZE,
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PM_FPGA_LOAD,
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PM_FPGA_GET_STATUS,
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PM_GET_CHIPID,
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PM_SECURE_RSA_AES,
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PM_SECURE_SHA,
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PM_SECURE_RSA,
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PM_PINCTRL_REQUEST,
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PM_PINCTRL_RELEASE,
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PM_PINCTRL_GET_FUNCTION,
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PM_PINCTRL_SET_FUNCTION,
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PM_PINCTRL_CONFIG_PARAM_GET,
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PM_PINCTRL_CONFIG_PARAM_SET,
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PM_IOCTL,
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/* API to query information from firmware */
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PM_QUERY_DATA,
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/* Clock control API functions */
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PM_CLOCK_ENABLE,
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PM_CLOCK_DISABLE,
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PM_CLOCK_GETSTATE,
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PM_CLOCK_SETDIVIDER,
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PM_CLOCK_GETDIVIDER,
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PM_CLOCK_SETPARENT = 43,
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PM_CLOCK_GETPARENT,
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PM_SECURE_IMAGE,
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/* FPGA PL Readback */
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PM_FPGA_READ,
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PM_SECURE_AES,
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/* PLL control API functions */
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PM_PLL_SET_PARAMETER,
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PM_PLL_GET_PARAMETER,
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PM_PLL_SET_MODE,
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PM_PLL_GET_MODE,
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/* PM Register Access API */
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PM_REGISTER_ACCESS,
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PM_EFUSE_ACCESS,
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PM_FPGA_GET_VERSION,
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PM_FPGA_GET_FEATURE_LIST,
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PM_FEATURE_CHECK = 63,
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PM_API_MAX = 74
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};
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enum pm_abort_reason {
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ABORT_REASON_WKUP_EVENT = 100,
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ABORT_REASON_PU_BUSY,
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ABORT_REASON_NO_PWRDN,
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ABORT_REASON_UNKNOWN,
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};
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enum pm_opchar_type {
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PM_OPCHAR_TYPE_POWER = 1,
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PM_OPCHAR_TYPE_TEMP,
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PM_OPCHAR_TYPE_LATENCY,
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};
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/*
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* Subsystem IDs
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*/
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typedef enum {
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XPM_SUBSYSID_PMC,
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XPM_SUBSYSID_PSM,
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XPM_SUBSYSID_APU,
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XPM_SUBSYSID_RPU0_LOCK,
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XPM_SUBSYSID_RPU0_0,
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XPM_SUBSYSID_RPU0_1,
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XPM_SUBSYSID_DDR0,
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XPM_SUBSYSID_ME,
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XPM_SUBSYSID_PL,
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XPM_SUBSYSID_MAX,
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} XPm_SubsystemId;
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/* TODO: move pm_ret_status from device specific location to common location */
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/**
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* enum pm_ret_status - enum represents the return status codes for a PM
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* operation.
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* @PM_RET_SUCCESS: success.
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* @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated).
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* @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated).
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* @PM_RET_ERROR_NOFEATURE: feature is not available.
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* @PM_RET_ERROR_INVALID_CRC: invalid crc in IPI communication.
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* @PM_RET_ERROR_NOT_ENABLED: feature is not enabled.
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* @PM_RET_ERROR_INTERNAL: internal error.
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* @PM_RET_ERROR_CONFLICT: conflict.
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* @PM_RET_ERROR_ACCESS: access rights violation.
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* @PM_RET_ERROR_INVALID_NODE: invalid node.
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* @PM_RET_ERROR_DOUBLE_REQ: duplicate request for same node.
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* @PM_RET_ERROR_ABORT_SUSPEND: suspend procedure has been aborted.
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* @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU.
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* @PM_RET_ERROR_NODE_USED: node is already in use.
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* @PM_RET_ERROR_NO_FEATURE: indicates that the requested feature is not
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* supported.
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*/
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enum pm_ret_status {
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PM_RET_SUCCESS,
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PM_RET_ERROR_ARGS = 1,
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PM_RET_ERROR_NOTSUPPORTED = 4,
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PM_RET_ERROR_NOFEATURE = 19,
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PM_RET_ERROR_INVALID_CRC = 301,
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PM_RET_ERROR_NOT_ENABLED = 29,
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PM_RET_ERROR_INTERNAL = 2000,
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PM_RET_ERROR_CONFLICT = 2001,
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PM_RET_ERROR_ACCESS = 2002,
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PM_RET_ERROR_INVALID_NODE = 2003,
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PM_RET_ERROR_DOUBLE_REQ = 2004,
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PM_RET_ERROR_ABORT_SUSPEND = 2005,
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PM_RET_ERROR_TIMEOUT = 2006,
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PM_RET_ERROR_NODE_USED = 2007,
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PM_RET_ERROR_NO_FEATURE = 2008
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};
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/*
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* Qids
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*/
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enum pm_query_id {
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XPM_QID_INVALID,
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XPM_QID_CLOCK_GET_NAME,
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XPM_QID_CLOCK_GET_TOPOLOGY,
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XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
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XPM_QID_CLOCK_GET_MUXSOURCES,
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XPM_QID_CLOCK_GET_ATTRIBUTES,
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XPM_QID_PINCTRL_GET_NUM_PINS,
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XPM_QID_PINCTRL_GET_NUM_FUNCTIONS,
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XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
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XPM_QID_PINCTRL_GET_FUNCTION_NAME,
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XPM_QID_PINCTRL_GET_FUNCTION_GROUPS,
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XPM_QID_PINCTRL_GET_PIN_GROUPS,
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XPM_QID_CLOCK_GET_NUM_CLOCKS,
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XPM_QID_CLOCK_GET_MAX_DIVISOR,
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XPM_QID_PLD_GET_PARENT,
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};
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#endif /* PM_DEFS_H */
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