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With the introduction of FEAT_RME MDCR_EL3 bits NSPB and NSPBE depend on each other. The enable code relies on the register being initialised to zero and omits to reset NSPBE. However, this is not obvious. Reset the bit explicitly to document this. Similarly, reset the STE bit , since it's part of the feature enablement. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I3714507bae10042cdccd2b7bc713b31d4cdeb02f
92 lines
2 KiB
C
92 lines
2 KiB
C
/*
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* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_features.h>
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#include <arch_helpers.h>
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#include <lib/el3_runtime/pubsub.h>
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#include <lib/extensions/spe.h>
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static inline void psb_csync(void)
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{
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/*
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* The assembler does not yet understand the psb csync mnemonic
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* so use the equivalent hint instruction.
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*/
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__asm__ volatile("hint #17");
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}
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void spe_init_el3(void)
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{
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uint64_t v;
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/*
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* MDCR_EL3.NSPB (ARM v8.2): SPE enabled in Non-secure state
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* and disabled in secure state. Accesses to SPE registers at
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* S-EL1 generate trap exceptions to EL3.
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*
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* MDCR_EL3.NSPBE: Profiling Buffer uses Non-secure Virtual Addresses.
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* When FEAT_RME is not implemented, this field is RES0.
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*
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* MDCR_EL3.EnPMSN (ARM v8.7): Do not trap access to PMSNEVFR_EL1
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* register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2 is implemented.
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* Setting this bit to 1 doesn't have any effect on it when
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* FEAT_SPEv1p2 not implemented.
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*/
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v = read_mdcr_el3();
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v |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
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v &= ~(MDCR_NSPBE_BIT);
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write_mdcr_el3(v);
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}
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void spe_init_el2_unused(void)
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{
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uint64_t v;
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/*
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* MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical
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* profiling controls to EL2.
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*
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* MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure
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* state. Accesses to profiling buffer controls at
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* Non-secure EL1 are not trapped to EL2.
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*/
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v = read_mdcr_el2();
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v &= ~MDCR_EL2_TPMS;
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v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1);
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write_mdcr_el2(v);
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}
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void spe_disable(void)
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{
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uint64_t v;
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/* Drain buffered data */
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psb_csync();
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dsbnsh();
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/* Disable profiling buffer */
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v = read_pmblimitr_el1();
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v &= ~(1ULL << 0);
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write_pmblimitr_el1(v);
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isb();
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}
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static void *spe_drain_buffers_hook(const void *arg)
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{
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if (!is_feat_spe_supported())
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return (void *)-1;
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/* Drain buffered data */
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psb_csync();
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dsbnsh();
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return (void *)0;
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}
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SUBSCRIBE_TO_EVENT(cm_entering_secure_world, spe_drain_buffers_hook);
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