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fix(cm): set MDCR_EL3.{NSPBE, STE} explicitly

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With the introduction of FEAT_RME MDCR_EL3 bits NSPB and NSPBE depend on
each other. The enable code relies on the register being initialised to
zero and omits to reset NSPBE. However, this is not obvious. Reset the
bit explicitly to document this.

Similarly, reset the STE bit , since it's part of the feature enablement.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3714507bae10042cdccd2b7bc713b31d4cdeb02f
This commit is contained in:
Boyan Karatotev 2023-02-13 16:38:37 +00:00 • committed by Jayanth Dodderi Chidanand
parent b48bd79073
commit 99506face1
5 changed files with 17 additions and 8 deletions
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8
include/arch/aarch32/arch.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -197,11 +197,11 @@
#define SDCR_SPD_LEGACY U(0x0)
#define SDCR_SPD_DISABLE U(0x2)
#define SDCR_SPD_ENABLE U(0x3)
#define SDCR_SCCD_BIT (U(1) << 23)
#define SDCR_TTRF_BIT (U(1) << 19)
#define SDCR_SPME_BIT (U(1) << 17)
#define SDCR_RESET_VAL U(0x0)
#define SDCR_TTRF_BIT (U(1) << 19)
#define SDCR_SCCD_BIT (U(1) << 23)
#define SDCR_MTPME_BIT (U(1) << 28)
#define SDCR_RESET_VAL U(0x0)
/* HSCTLR definitions */
#define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \

1
include/arch/aarch64/arch.h
View file

@ -612,6 +612,7 @@
#define MDCR_SPD32_ENABLE ULL(0x3)
#define MDCR_NSPB(x) ((x) << 12)
#define MDCR_NSPB_EL1 ULL(0x3)
#define MDCR_NSPBE_BIT (ULL(1) << 11)
#define MDCR_TDOSA_BIT (ULL(1) << 10)
#define MDCR_TDA_BIT (ULL(1) << 9)
#define MDCR_TPM_BIT (ULL(1) << 6)

6
lib/extensions/spe/spe.c
View file

@ -26,10 +26,13 @@ void spe_init_el3(void)
uint64_t v;
/*
* MDCR_EL2.NSPB (ARM v8.2): SPE enabled in Non-secure state
* MDCR_EL3.NSPB (ARM v8.2): SPE enabled in Non-secure state
* and disabled in secure state. Accesses to SPE registers at
* S-EL1 generate trap exceptions to EL3.
*
* MDCR_EL3.NSPBE: Profiling Buffer uses Non-secure Virtual Addresses.
* When FEAT_RME is not implemented, this field is RES0.
*
* MDCR_EL3.EnPMSN (ARM v8.7): Do not trap access to PMSNEVFR_EL1
* register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2 is implemented.
* Setting this bit to 1 doesn't have any effect on it when
@ -37,6 +40,7 @@ void spe_init_el3(void)
*/
v = read_mdcr_el3();
v |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
v &= ~(MDCR_NSPBE_BIT);
write_mdcr_el3(v);
}

4
lib/extensions/trf/aarch32/trf.c
View file

@ -16,9 +16,9 @@ void trf_init_el3(void)
/*
* Allow access of trace filter control registers from
* non-monitor mode
* non-monitor mode.
*/
val = read_sdcr();
val &= ~SDCR_TTRF_BIT;
val &= ~(SDCR_TTRF_BIT);
write_sdcr(val);
}

6
lib/extensions/trf/aarch64/trf.c
View file

@ -14,12 +14,16 @@ void trf_init_el3(void)
u_register_t val;
/*
* MDCR_EL3.STE = b0
* Trace prohibited in Secure state unless overridden by the
* IMPLEMENTATION DEFINED authentication interface.
*
* MDCR_EL3.TTRF = b0
* Allow access of trace filter control registers from NS-EL2
* and NS-EL1 when NS-EL2 is implemented but not used
*/
val = read_mdcr_el3();
val &= ~MDCR_TTRF_BIT;
val &= ~(MDCR_STE_BIT | MDCR_TTRF_BIT);
write_mdcr_el3(val);
}