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0cc7aa8964
At present, the function provided by the translation library to enable
MMU constructs appropriate values for translation library, and programs
them to the right registers. The construction of initial values,
however, is only required once as both the primary and secondaries
program the same values.
Additionally, the MMU-enabling function is written in C, which means
there's an active stack at the time of enabling MMU. On some systems,
like Arm DynamIQ, having active stack while enabling MMU during warm
boot might lead to coherency problems.
This patch addresses both the above problems by:
- Splitting the MMU-enabling function into two: one that sets up
values to be programmed into the registers, and another one that
takes the pre-computed values and writes to the appropriate
registers. With this, the primary effectively calls both functions
to have the MMU enabled, but secondaries only need to call the
latter.
- Rewriting the function that enables MMU in assembly so that it
doesn't use stack.
This patch fixes a bunch of MISRA issues on the way.
Change-Id: I0faca97263a970ffe765f0e731a1417e43fbfc45
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
67 lines
2.3 KiB
C
67 lines
2.3 KiB
C
/*
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* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __XLAT_MMU_HELPERS_H__
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#define __XLAT_MMU_HELPERS_H__
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/*
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* The following flags are passed to enable_mmu_xxx() to override the default
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* values used to program system registers while enabling the MMU.
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*/
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/*
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* When this flag is used, all data access to Normal memory from this EL and all
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* Normal memory accesses to the translation tables of this EL are non-cacheable
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* for all levels of data and unified cache until the caches are enabled by
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* setting the bit SCTLR_ELx.C.
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*/
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#define DISABLE_DCACHE (U(1) << 0)
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/*
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* Mark the translation tables as non-cacheable for the MMU table walker, which
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* is a different observer from the PE/CPU. If the flag is not specified, the
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* tables are cacheable for the MMU table walker.
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*
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* Note that, as far as the PE/CPU observer is concerned, the attributes used
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* are the ones specified in the translation tables themselves. The MAIR
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* register specifies the cacheability through the field AttrIndx of the lower
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* attributes of the translation tables. The shareability is specified in the SH
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* field of the lower attributes.
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*
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* The MMU table walker uses the attributes specified in the fields ORGNn, IRGNn
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* and SHn of the TCR register to access the translation tables.
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*
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* The attributes specified in the TCR register and the tables can be different
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* as there are no checks to prevent that. Special care must be taken to ensure
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* that there aren't mismatches. The behaviour in that case is described in the
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* sections 'Mismatched memory attributes' in the ARMv8 ARM.
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*/
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#define XLAT_TABLE_NC (U(1) << 1)
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#ifndef __ASSEMBLY__
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#include <sys/types.h>
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#ifdef AARCH32
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/* AArch32 specific translation table API */
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void enable_mmu_secure(unsigned int flags);
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void enable_mmu_direct(unsigned int flags);
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#else
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/* AArch64 specific translation table APIs */
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void enable_mmu_el1(unsigned int flags);
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void enable_mmu_el3(unsigned int flags);
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void enable_mmu_direct_el1(unsigned int flags);
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void enable_mmu_direct_el3(unsigned int flags);
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#endif /* AARCH32 */
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int xlat_arch_is_granule_size_supported(size_t size);
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size_t xlat_arch_get_max_supported_granule_size(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __XLAT_MMU_HELPERS_H__ */
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