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fded839285
Neoverse-N3 erratum 3699563 that applies to r0p0 is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-3050973/latest/ Change-Id: I77aaf8ae0afff3adde9a85f4a1a13ac9d1daf0af Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
75 lines
2.2 KiB
ArmAsm
75 lines
2.2 KiB
ArmAsm
/*
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* Copyright (c) 2023-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <neoverse_n3.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse-N3 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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.global check_erratum_neoverse_n3_3699563
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add_erratum_entry neoverse_n3, ERRATUM(3699563), ERRATA_N3_3699563, NO_APPLY_AT_RESET
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check_erratum_ls neoverse_n3, ERRATUM(3699563), CPU_REV(0, 0)
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cpu_reset_func_start neoverse_n3
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/* Disable speculative loads */
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msr SSBS, xzr
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#if NEOVERSE_Nx_EXTERNAL_LLC
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/* Some systems may have External LLC, core needs to be made aware */
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sysreg_bit_set NEOVERSE_N3_CPUECTLR_EL1, NEOVERSE_N3_CPUECTLR_EL1_EXTLLC_BIT
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#endif
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cpu_reset_func_end neoverse_n3
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func neoverse_n3_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set NEOVERSE_N3_CPUPWRCTLR_EL1, NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc neoverse_n3_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Neoverse-N3 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_n3_regs, "aS"
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neoverse_n3_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_n3_cpu_reg_dump
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adr x6, neoverse_n3_regs
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mrs x8, NEOVERSE_N3_CPUECTLR_EL1
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ret
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endfunc neoverse_n3_cpu_reg_dump
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declare_cpu_ops neoverse_n3, NEOVERSE_N3_MIDR, \
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neoverse_n3_reset_func, \
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neoverse_n3_core_pwr_dwn
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