Sieu Mun Tang bf3877e072 fix(intel): handle cold reset via physical reset switch ... On the Agilex5 platform when cold reset is issued via CLI application in the OS, it is received in the BL31 via a SMC call and handled accordingly like flush/invalidate the caches. However, when the cold reset is issued via an external switch these handlings are missed. This patch addresses those missed cache operations. Also, this patch is to restoring SCR_EL3 NS bit to its previous value in order to avoid unintended behavior especially if subsequent code expects the SCR_EL3 register to be in its original configuration. Change-Id: I9737f2db649e483ba61fffa6eeb0b56a9d15074a Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>		2024-12-23 17:52:41 +08:00
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include	Merge "fix(intel): add in JTAG ID for Linux FCS" into integration	2024-10-28 23:12:04 +01:00
soc	fix(intel): handle cold reset via physical reset switch	2024-12-23 17:52:41 +08:00
bl2_plat_setup.c	Merge "fix(intel): refactor SDMMC driver for Altera products" into integration	2024-10-28 23:03:29 +01:00
bl31_plat_setup.c	fix(intel): handle cold reset via physical reset switch	2024-12-23 17:52:41 +08:00
platform.mk	Merge "fix(intel): add in JTAG ID for Linux FCS" into integration	2024-10-28 23:12:04 +01:00