Jayanth Dodderi Chidanand f4303d05ea feat(cm): handle asymmetry for FEAT_TCR2 ... With introduction of FEAT_STATE_CHECK_ASYMMETRIC, the asymmetry of cores can be handled. FEAT_TCR2 is one of the features which can be asymmetric across cores and the respective support is added here. Adding a function to handle this asymmetry by re-visting the feature presence on running core. There are two possible cases: - If the primary core has the feature and secondary does not have it then the feature is disabled. - If the primary does not have the feature and secondary has it then, the feature need to be enabled in secondary cores. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: I73a70891d52268ddfa4effe40edf04115f5821ca		2024-09-05 16:28:23 +01:00
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amu	refactor(cm): move EL3 registers to global context	2023-10-31 11:18:42 +00:00
brbe	feat(cm): context switch MDCR_EL3 register	2024-06-25 13:50:32 +01:00
debug	feat(debugv8p9): add support for FEAT_Debugv8p9	2024-07-18 13:49:43 -05:00
fgt	feat(fgt2): add support for FEAT_FGT2	2024-07-18 13:49:43 -05:00
mpam	refactor(cm): move MPAM3_EL3 reg to per world context	2023-12-21 12:37:21 +00:00
pauth	chore(pauth): remove redundant pauth_disable_el3() call	2023-04-28 08:09:14 +01:00
pmuv3	refactor(cm): remove el1 context when SPMD_SPM_AT_SEL2=1	2024-08-21 16:35:27 +01:00
ras	chore: update to use Arm word across TF-A	2023-08-08 15:12:30 +01:00
sme	refactor(cpufeat): add macro to simplify is_feat_xx_present	2024-05-02 12:16:16 -05:00
spe	feat(spe): introduce spe_disable() function	2024-07-29 20:34:18 +01:00
sve	refactor(cm): move EL3 registers to global context	2023-10-31 11:18:42 +00:00
sys_reg_trace	refactor(cm): move EL3 registers to global context	2023-10-31 11:18:42 +00:00
tcr	feat(cm): handle asymmetry for FEAT_TCR2	2024-09-05 16:28:23 +01:00
trbe	feat(trbe): introduce trbe_disable() function	2024-07-29 20:35:14 +01:00
trf	feat(cm): context switch MDCR_EL3 register	2024-06-25 13:50:32 +01:00