John Powell f2bd352820 fix(errata): workaround for Cortex-A510 erratum 2971420 ... Cortex-A510 erratum 2971420 applies to revisions r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and is still open. Under some conditions, data might be corrupted if Trace Buffer Extension (TRBE) is enabled. The workaround is to disable trace collection via TRBE by programming MDCR_EL3.NSTB[1] to the opposite value of SCR_EL3.NS on a security state switch. Since we only enable TRBE for non-secure world, the workaround is to disable TRBE by setting the NSTB field to 00 so accesses are trapped to EL3 and secure state owns the buffer. SDEN: https://developer.arm.com/documentation/SDEN-1873361/latest/ Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ia77051f6b64c726a8c50596c78f220d323ab7d97		2025-03-17 19:04:54 +01:00
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aarch32	perf(cpus): inline the reset function	2025-02-24 09:36:10 +00:00
aarch64	fix(errata): workaround for Cortex-A510 erratum 2971420	2025-03-17 19:04:54 +01:00
cpu-ops.mk	fix(errata): workaround for Cortex-A510 erratum 2971420	2025-03-17 19:04:54 +01:00
errata_common.c	fix(errata): workaround for Cortex-A510 erratum 2971420	2025-03-17 19:04:54 +01:00
errata_report.c	refactor(cpus): directly invoke errata reporter	2024-07-26 11:19:52 +01:00