Louis Mayencourt f1be00da0b Use correct type when reading SCR register ... The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2020-01-28 11:10:48 +00:00
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aarch64	Prevent speculative execution past ERET	2020-01-22 21:42:51 +00:00
bl31.ld.S	bl31: Split into two separate memory regions	2019-12-29 12:00:40 -06:00
bl31.mk	Merge "debugfs: add 9p device interface" into integration	2019-12-20 18:10:50 +00:00
bl31_context_mgmt.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
bl31_main.c	Refactor ARMv8.3 Pointer Authentication support code	2019-09-13 14:11:59 +01:00
ehf.c	Minor changes to documentation and comments	2019-02-28 13:35:21 +00:00
interrupt_mgmt.c	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00