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https://github.com/ARM-software/arm-trusted-firmware.git
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85f199b774
Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated. This patch adds the initial platform support for AST2700 and also updates the documents. Change-Id: I1796f7aae5ed2d1799e91fabb8949607959cd9b3 Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
63 lines
1.2 KiB
C
63 lines
1.2 KiB
C
/*
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* Copyright (c) 2023, Aspeed Technology Inc.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <common/debug.h>
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#include <drivers/arm/gicv3.h>
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#include <drivers/console.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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static uintptr_t sec_ep;
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static int plat_pwr_domain_on(u_register_t mpidr)
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{
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unsigned int cpu = plat_core_pos_by_mpidr(mpidr);
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uintptr_t ep_reg;
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switch (cpu) {
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case 1U:
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ep_reg = SCU_CPU_SMP_EP1;
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break;
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case 2U:
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ep_reg = SCU_CPU_SMP_EP2;
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break;
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case 3U:
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ep_reg = SCU_CPU_SMP_EP3;
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break;
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default:
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return PSCI_E_INVALID_PARAMS;
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}
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mmio_write_64(ep_reg, sec_ep);
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dsbsy();
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sev();
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return PSCI_E_SUCCESS;
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}
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static void plat_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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static const plat_psci_ops_t plat_psci_ops = {
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.pwr_domain_on = plat_pwr_domain_on,
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.pwr_domain_on_finish = plat_pwr_domain_on_finish,
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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sec_ep = sec_entrypoint;
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*psci_ops = &plat_psci_ops;
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return 0;
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}
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