mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-29 08:40:03 +00:00
cd7d6b0eb1
The size increase after enabling options related to ARMv8.3-PAuth is:
+----------------------------+-------+-------+-------+--------+
| | text | bss | data | rodata |
+----------------------------+-------+-------+-------+--------+
| CTX_INCLUDE_PAUTH_REGS = 1 | +108 | +192 | +0 | +0 |
| | 0.5% | 0.8% | | |
+----------------------------+-------+-------+-------+--------+
| ENABLE_PAUTH = 1 | +748 | +192 | +16 | +0 |
| | 3.7% | 0.8% | 7.0% | |
+----------------------------+-------+-------+-------+--------+
Results calculated with the following build configuration:
make PLAT=fvp SPD=tspd DEBUG=1 \
SDEI_SUPPORT=1 \
EL3_EXCEPTION_HANDLING=1 \
TSP_NS_INTR_ASYNC_PREEMPT=1 \
CTX_INCLUDE_PAUTH_REGS=1 \
ENABLE_PAUTH=1
Change-Id: I3a7d02feb6a6d212be32a01432b0c7c1a261f567
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
98 lines
2.7 KiB
ArmAsm
98 lines
2.7 KiB
ArmAsm
/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <context.h>
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#include <el3_common_macros.S>
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#include <smccc_helpers.h>
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#include <smccc_macros.S>
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.globl bl1_vector_table
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.globl bl1_entrypoint
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/* -----------------------------------------------------
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* Setup the vector table to support SVC & MON mode.
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* -----------------------------------------------------
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*/
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vector_base bl1_vector_table
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b bl1_entrypoint
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b report_exception /* Undef */
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b bl1_aarch32_smc_handler /* SMC call */
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b report_exception /* Prefetch abort */
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b report_exception /* Data abort */
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b report_exception /* Reserved */
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b report_exception /* IRQ */
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b report_exception /* FIQ */
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/* -----------------------------------------------------
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* bl1_entrypoint() is the entry point into the trusted
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* firmware code when a cpu is released from warm or
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* cold reset.
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* -----------------------------------------------------
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*/
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func bl1_entrypoint
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/* ---------------------------------------------------------------------
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* If the reset address is programmable then bl1_entrypoint() is
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* executed only on the cold boot path. Therefore, we can skip the warm
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* boot mailbox mechanism.
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* ---------------------------------------------------------------------
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*/
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el3_entrypoint_common \
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_init_sctlr=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=bl1_vector_table
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/* -----------------------------------------------------
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* Perform BL1 setup
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* -----------------------------------------------------
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*/
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bl bl1_setup
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/* -----------------------------------------------------
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* Jump to main function.
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* -----------------------------------------------------
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*/
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bl bl1_main
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/* -----------------------------------------------------
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* Jump to next image.
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* -----------------------------------------------------
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*/
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/*
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* Get the smc_context for next BL image,
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* program the gp/system registers and save it in `r4`.
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*/
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bl smc_get_next_ctx
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mov r4, r0
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/* Only turn-off MMU if going to secure world */
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ldr r5, [r4, #SMC_CTX_SCR]
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tst r5, #SCR_NS_BIT
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bne skip_mmu_off
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/*
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* MMU needs to be disabled because both BL1 and BL2/BL2U execute
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* in PL1, and therefore share the same address space.
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* BL2/BL2U will initialize the address space according to its
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* own requirement.
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*/
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bl disable_mmu_icache_secure
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stcopr r0, TLBIALL
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dsb sy
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isb
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skip_mmu_off:
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/* Restore smc_context from `r4` and exit secure monitor mode. */
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mov r0, r4
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monitor_exit
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endfunc bl1_entrypoint
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