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https://github.com/ARM-software/arm-trusted-firmware.git
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05cc21de5d
Add QoS support for RZ/G2E SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Change-Id: I2c4373807ab8c550d86d6abc97f5b01f2fb78fb3
105 lines
3.4 KiB
C
105 lines
3.4 KiB
C
/*
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* Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QOS_COMMON_H
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#define QOS_COMMON_H
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#define RCAR_REF_DEFAULT 0U
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/* define used for get_refperiod. */
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/* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */
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#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */
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#define REFPERIOD_CYCLE /* unit:ns */ \
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((126U * BASE_SUB_SLOT_NUM * 1000U) / 400U)
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#else /* REF option */
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#define REFPERIOD_CYCLE /* unit:ns */ \
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((252U * BASE_SUB_SLOT_NUM * 1000U) / 400U)
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#endif
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M)
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/* define used for G2M */
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#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
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#define SUB_SLOT_CYCLE_G2M_11 0x7EU /* 126 */
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#define SUB_SLOT_CYCLE_G2M_30 0x7EU /* 126 */
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#else /* REF 3.9usec */
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#define SUB_SLOT_CYCLE_G2M_11 0xFCU /* 252 */
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#define SUB_SLOT_CYCLE_G2M_30 0xFCU /* 252 */
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#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
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#define SL_INIT_SSLOTCLK_G2M_11 (SUB_SLOT_CYCLE_G2M_11 - 1U)
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#define SL_INIT_SSLOTCLK_G2M_30 (SUB_SLOT_CYCLE_G2M_30 - 1U)
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#define QOSWT_WTSET0_CYCLE_G2M_11 /* unit:ns */ \
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((SUB_SLOT_CYCLE_G2M_11 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
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#define QOSWT_WTSET0_CYCLE_G2M_30 /* unit:ns */ \
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((SUB_SLOT_CYCLE_G2M_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
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#endif
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N)
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/* define used for G2N */
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#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
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#define SUB_SLOT_CYCLE_G2N 0x7EU /* 126 */
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#else /* REF 3.9usec */
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#define SUB_SLOT_CYCLE_G2N 0xFCU /* 252 */
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#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
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#define SL_INIT_SSLOTCLK_G2N (SUB_SLOT_CYCLE_G2N - 1U)
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#define QOSWT_WTSET0_CYCLE_G2N /* unit:ns */ \
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((SUB_SLOT_CYCLE_G2N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
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#endif /* (RCAR_LSI == RZ_G2N) */
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H)
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/* define used for G2H */
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#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
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#define SUB_SLOT_CYCLE_G2H 0x7EU /* 126 */
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#else /* REF 3.9usec */
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#define SUB_SLOT_CYCLE_G2H 0xFCU /* 252 */
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#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
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#define SL_INIT_SSLOTCLK_G2H (SUB_SLOT_CYCLE_G2H - 1U)
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#define QOSWT_WTSET0_CYCLE_G2H /* unit:ns */ \
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((SUB_SLOT_CYCLE_G2H * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
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#endif
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2E)
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/* define used for G2E */
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#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */
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#define SUB_SLOT_CYCLE_G2E 0xAFU /* 175 */
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#else /* REF 7.8usec */
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#define SUB_SLOT_CYCLE_G2E 0x15EU /* 350 */
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#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
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#define OPERATING_FREQ_G2E 266U /* MHz */
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#define SL_INIT_SSLOTCLK_G2E (SUB_SLOT_CYCLE_G2E - 1U)
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#endif
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#define OPERATING_FREQ 400U /* MHz */
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#define BASE_SUB_SLOT_NUM 0x6U
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#define SUB_SLOT_CYCLE 0x7EU /* 126 */
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#define QOSWT_WTSET0_CYCLE /* unit:ns */ \
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((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
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#define SL_INIT_REFFSSLOT (0x3U << 24U)
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#define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U)
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#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE - 1U)
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typedef struct {
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uintptr_t addr;
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uint64_t value;
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} mstat_slot_t;
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struct rcar_gen3_dbsc_qos_settings {
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uint32_t reg;
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uint32_t val;
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};
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extern uint32_t qos_init_ddr_ch;
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extern uint8_t qos_init_ddr_phyvalid;
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void rzg_qos_dbsc_setting(const struct rcar_gen3_dbsc_qos_settings *qos,
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unsigned int qos_size, bool dbsc_wren);
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#endif /* QOS_COMMON_H */
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