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e373b6a28c
The logic that initializes the BL32 entry point data structure should only be executed if we are in fact loading OP-TEE, and not if BL32_BASE is set for other reasons (i.e., when enabling SPM) Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
45 lines
1.4 KiB
Makefile
45 lines
1.4 KiB
Makefile
#
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# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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override RESET_TO_BL31 := 1
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override MULTI_CONSOLE_API := 1
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override PROGRAMMABLE_RESET_ADDRESS := 1
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override USE_COHERENT_MEM := 1
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override SEPARATE_CODE_AND_RODATA := 1
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override ENABLE_SVE_FOR_NS := 0
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# Enable workarounds for selected Cortex-A53 erratas.
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ERRATA_A53_855873 := 1
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# Libraries
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include lib/xlat_tables_v2/xlat_tables.mk
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PLAT_PATH := plat/socionext/synquacer
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PLAT_INCLUDES := -I$(PLAT_PATH)/include \
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-I$(PLAT_PATH)/drivers/scpi \
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-I$(PLAT_PATH)/drivers/mhu
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PLAT_BL_COMMON_SOURCES += $(PLAT_PATH)/sq_helpers.S \
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drivers/arm/pl011/aarch64/pl011_console.S \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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${XLAT_TABLES_LIB_SRCS}
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BL31_SOURCES += drivers/arm/ccn/ccn.c \
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drivers/arm/gic/common/gic_common.c \
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drivers/arm/gic/v3/gicv3_helpers.c \
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drivers/arm/gic/v3/gicv3_main.c \
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lib/cpus/aarch64/cortex_a53.S \
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plat/common/plat_gicv3.c \
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plat/common/plat_psci_common.c \
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$(PLAT_PATH)/sq_bl31_setup.c \
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$(PLAT_PATH)/sq_ccn.c \
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$(PLAT_PATH)/sq_topology.c \
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$(PLAT_PATH)/sq_psci.c \
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$(PLAT_PATH)/sq_gicv3.c \
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$(PLAT_PATH)/sq_xlat_setup.c \
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$(PLAT_PATH)/drivers/scpi/sq_scpi.c \
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$(PLAT_PATH)/drivers/mhu/sq_mhu.c
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