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8b779620d3
In order for the symbol table in the ELF file to contain the size of functions written in assembly, it is necessary to report it to the assembler using the .size directive. To fulfil the above requirements, this patch introduces an 'endfunc' macro which contains the .endfunc and .size directives. It also adds a .func directive to the 'func' assembler macro. The .func/.endfunc have been used so the assembler can fail if endfunc is omitted. Fixes ARM-Software/tf-issues#295 Change-Id: If8cb331b03d7f38fe7e3694d4de26f1075b278fc Signed-off-by: Kévin Petit <kevin.petit@arm.com>
168 lines
5.5 KiB
ArmAsm
168 lines
5.5 KiB
ArmAsm
/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <platform_def.h>
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#include <psci.h>
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.globl psci_do_pwrdown_cache_maintenance
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.globl psci_do_pwrup_cache_maintenance
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/* -----------------------------------------------------------------------
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* void psci_do_pwrdown_cache_maintenance(uint32_t affinity level);
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*
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* This function performs cache maintenance if the specified affinity
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* level is the equal to the level of the highest affinity instance which
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* will be/is physically powered off. The levels of cache affected are
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* determined by the affinity level which is passed as the argument i.e.
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* level 0 results in a flush of the L1 cache. Both the L1 and L2 caches
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* are flushed for a higher affinity level.
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*
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* Additionally, this function also ensures that stack memory is correctly
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* flushed out to avoid coherency issues due to a change in its memory
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* attributes after the data cache is disabled.
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* -----------------------------------------------------------------------
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*/
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func psci_do_pwrdown_cache_maintenance
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stp x29, x30, [sp,#-16]!
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stp x19, x20, [sp,#-16]!
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mov x19, x0
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bl psci_get_max_phys_off_afflvl
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#if ASM_ASSERTION
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cmp x0, #PSCI_INVALID_DATA
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ASM_ASSERT(ne)
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#endif
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cmp x0, x19
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b.ne 1f
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/* ---------------------------------------------
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* Determine to how many levels of cache will be
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* subject to cache maintenance. Affinity level
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* 0 implies that only the cpu is being powered
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* down. Only the L1 data cache needs to be
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* flushed to the PoU in this case. For a higher
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* affinity level we are assuming that a flush
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* of L1 data and L2 unified cache is enough.
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* This information should be provided by the
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* platform.
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* ---------------------------------------------
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*/
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cmp x0, #MPIDR_AFFLVL0
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b.eq do_core_pwr_dwn
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bl prepare_cluster_pwr_dwn
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b do_stack_maintenance
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do_core_pwr_dwn:
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bl prepare_core_pwr_dwn
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/* ---------------------------------------------
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* Do stack maintenance by flushing the used
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* stack to the main memory and invalidating the
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* remainder.
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* ---------------------------------------------
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*/
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do_stack_maintenance:
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mrs x0, mpidr_el1
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bl platform_get_stack
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/* ---------------------------------------------
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* Calculate and store the size of the used
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* stack memory in x1.
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* ---------------------------------------------
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*/
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mov x19, x0
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mov x1, sp
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sub x1, x0, x1
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mov x0, sp
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bl flush_dcache_range
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/* ---------------------------------------------
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* Calculate and store the size of the unused
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* stack memory in x1. Calculate and store the
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* stack base address in x0.
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* ---------------------------------------------
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*/
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sub x0, x19, #PLATFORM_STACK_SIZE
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sub x1, sp, x0
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bl inv_dcache_range
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1:
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ldp x19, x20, [sp], #16
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ldp x29, x30, [sp], #16
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ret
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endfunc psci_do_pwrdown_cache_maintenance
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/* -----------------------------------------------------------------------
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* void psci_do_pwrup_cache_maintenance(void);
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*
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* This function performs cache maintenance after this cpu is powered up.
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* Currently, this involves managing the used stack memory before turning
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* on the data cache.
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* -----------------------------------------------------------------------
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*/
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func psci_do_pwrup_cache_maintenance
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stp x29, x30, [sp,#-16]!
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/* ---------------------------------------------
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* Ensure any inflight stack writes have made it
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* to main memory.
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* ---------------------------------------------
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*/
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dmb st
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/* ---------------------------------------------
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* Calculate and store the size of the used
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* stack memory in x1. Calculate and store the
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* stack base address in x0.
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* ---------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl platform_get_stack
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mov x1, sp
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sub x1, x0, x1
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mov x0, sp
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bl inv_dcache_range
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/* ---------------------------------------------
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* Enable the data cache.
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* ---------------------------------------------
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*/
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mrs x0, sctlr_el3
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orr x0, x0, #SCTLR_C_BIT
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msr sctlr_el3, x0
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isb
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ldp x29, x30, [sp], #16
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ret
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endfunc psci_do_pwrup_cache_maintenance
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