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https://github.com/ARM-software/arm-trusted-firmware.git
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a32a77f9c7
gpt_runtime_init() now takes the bitlock array's address and size as argument. Rather than reserving space at the end of the L0 GPT for storing bitlocks, allocate a static array and pass its address to gpt_runtime_init(). This frees up a little bit of space formerly reserved for alignment of the GPT. Change-Id: I48a1a2bc230f64e13e3ed08b18ebdc2d387d77d0 Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
67 lines
2 KiB
C
67 lines
2 KiB
C
/*
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* Copyright (c) 2024-2025, Linaro Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QEMU_PAS_DEF_H
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#define QEMU_PAS_DEF_H
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#include <lib/gpt_rme/gpt_rme.h>
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#include "platform_def.h"
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/*****************************************************************************
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* PAS regions used to initialize the Granule Protection Table (GPT)
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****************************************************************************/
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/* EL3 SRAM */
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#define QEMU_PAS_ROOT_BASE (BL32_MEM_BASE + BL32_MEM_SIZE)
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#define QEMU_PAS_ROOT_SIZE (BL_RAM_SIZE - \
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(BL32_MEM_SIZE + RME_GPT_DRAM_SIZE))
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/* Secure DRAM */
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#define QEMU_PAS_SEC_BASE BL32_MEM_BASE /* BL32_SRAM_BASE */
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#define QEMU_PAS_SEC_SIZE BL32_MEM_SIZE
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/* GPTs */
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#define QEMU_PAS_GPT_BASE RME_GPT_DRAM_BASE /* PLAT_QEMU_L0_GPT_BASE */
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#define QEMU_PAS_GPT_SIZE RME_GPT_DRAM_SIZE
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/* RMM */
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#define QEMU_PAS_RMM_BASE RMM_BASE
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#define QEMU_PAS_RMM_SIZE PLAT_QEMU_RMM_SIZE
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/* Shared area between EL3 and RMM */
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#define QEMU_PAS_RMM_SHARED_BASE RMM_SHARED_BASE
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#define QEMU_PAS_RMM_SHARED_SIZE RMM_SHARED_SIZE
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#define QEMU_PAS_ROOT GPT_MAP_REGION_GRANULE(QEMU_PAS_ROOT_BASE, \
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QEMU_PAS_ROOT_SIZE, \
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GPT_GPI_ROOT)
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#define QEMU_PAS_SECURE GPT_MAP_REGION_GRANULE(QEMU_PAS_SEC_BASE, \
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QEMU_PAS_SEC_SIZE, \
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GPT_GPI_SECURE)
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#define QEMU_PAS_GPTS GPT_MAP_REGION_GRANULE(QEMU_PAS_GPT_BASE, \
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QEMU_PAS_GPT_SIZE, \
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GPT_GPI_ROOT)
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/*
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* NS0 base address and size are fetched from the DT at runtime.
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* See bl31_adjust_pas_regions() for details
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*/
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#define QEMU_PAS_NS0 GPT_MAP_REGION_GRANULE(0, 0, GPT_GPI_NS)
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#define QEMU_PAS_REALM GPT_MAP_REGION_GRANULE(QEMU_PAS_RMM_BASE, \
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QEMU_PAS_RMM_SIZE + \
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QEMU_PAS_RMM_SHARED_SIZE, \
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GPT_GPI_REALM)
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/* Cover 4TB with L0GTP */
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#define PLAT_QEMU_GPCCR_PPS GPCCR_PPS_4TB
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#define PLAT_QEMU_PPS SZ_4T
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/* GPT Configuration options */
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#define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS
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#endif /* QEMU_PAS_DEF_H */
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